Patents Assigned to LSI Logic
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Patent number: 6292855Abstract: A set of registers are provided for a protocol engine driving I/O transactions requested by a host. A fixed set of defined data elements are determined for the protocol under which the I/O transaction is to be performed. Each register maps to a data structure base address or to a different data element offset or byte count. During initialization, the registers are programmed by an operating system device driver with offsets from a base address and byte counts for each data element within the defined set as those data elements are found within an operating system specific data structure for the I/O transaction, although data elements having a fixed size for each operating system may not require the byte count to be specified. For each I/O transaction requested, the base address in the host memory of the operating system specific data structure is programmed by the device driver into a register.Type: GrantFiled: December 18, 1998Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventors: Russell A. Johnson, Andrew C. Brown, Stephen B. Johnson
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Patent number: 6292125Abstract: A digital-to-analog converter (“DAC”) and method for digital-to-analog conversion is disclosed. The DAC generally comprises a plurality of analog weights, a weight table adapted to store digital sizes of the plurality of analog weights, and a converter for searching for selected weights from the plurality of analog weights using the digital sizes stored in the weight table and for mapping a binary input to the selected analog weights. The digital sizes of all except for at least two of the analog weights are successively approximated using the assigned sizes of at least two of the analog weights. The method for digital-to-analog conversion, comprising receiving the binary input, searching for selected weights from analog weights using a weight table storing digital sizes of the analog weights, mapping the binary input to the selected weights, and outputting a sum of the selected analog weights.Type: GrantFiled: September 29, 1999Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventor: Cormac S. Conroy
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Patent number: 6292224Abstract: An improved method for generating an NTSC compatible color television video signal having a main carrier signal and a color subcarrier signal 3,579,545 Hz above the main carrier signal. The main carrier signal is modulated by a luminance signal, while the color subcarrier is modulated in quadrature with color difference signals. The luminance and color difference signals provide 525 scan lines of picture frame information at a rate of 29.97 frames per second so that the color subcarrier has 227.5 cycles for each scan line, resulting in 119,437.5 color subcarrier cycles per frame. The additional half cycle causes a subcarrier phase inversion from frame to frame, which produces undesirable dot-crawl. The improvement comprises incrementing the phase of the color subcarrier by a fixed increment at a number of predetermined intervals in each picture frame, to produce a total phase shift which prevents the phase inversion. The total phase shift is an odd-half-multiple of a color subcarrier cycle.Type: GrantFiled: May 16, 1997Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventor: Brian K. Ogilvie
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Patent number: 6292522Abstract: A phase-locked loop cell includes a voltage-controlled oscillator adapted to produce an oscillating signal. A test input to the phase-locked loop is adapted to cause the voltage-controlled oscillator to generate a test oscillating signal. A frequency decoder is coupled to the output of the voltage controlled oscillator and is adapted to provide a voltage related to the frequency of the test oscillating signal.Type: GrantFiled: November 13, 1997Date of Patent: September 18, 2001Assignee: LSI Logic CorporationInventors: Edward Jewjing Jeng, Benedict Man-Fui Lok
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Patent number: 6289445Abstract: A circuit and method is provided which allows a microprocessor to implement speculative load instructions with implicit exception checking. In one embodiment of the method, exception information is generated in response to a memory access exception caused by a speculative load instruction for loading one of a plurality of first registers with data from memory. The exception information, once generated, is stored within one of a plurality of second registers. Each of the second registers corresponds to at least one of the plurality of first registers and is configured to store exception information. Thereafter, an instruction for operating on data stored in a first register is received and decoded by the microprocessor. In response, a second register corresponding to the first register is accessed. If this second register contains exception information, then the microprocessor initiates the exception routine.Type: GrantFiled: July 21, 1998Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventor: Hartvig Ekner
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Patent number: 6288454Abstract: A method of creating a layer-to-layer alignment mark in a semiconductor wafer includes the step of depositing a first conductor layer on a substrate associated with the semiconductor wafer. The method also includes the step of fabricating a number of alignment trenches in the first conductor layer. Moreover, the method includes the step of depositing a first insulator layer on the first conductor layer so as to fill the number of alignment trenches. Yet further, the method includes the step of removing material associated with the first insulator layer from the number of alignment trenches such that an upper surface of the first conductor layer and an upper surface of the first insulator layer define a first alignment step feature which possesses a predetermined height. The method also includes the step of depositing a second conductor layer on the semiconductor wafer subsequent to the removing step. A semiconductor wafer is also disclosed.Type: GrantFiled: June 23, 2000Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventors: Derryl D. J. Allman, Curtis C. Hainds, Charles W. Jurgensen, Brian R. Lee
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Patent number: 6289498Abstract: A method of fabricating an integrated circuit chip (IC), said method comprising the steps of defining the IC at the RTL code level, translating said RTL code into a generic netlist description, generating logic synthesis tool scripts based on said generic netlist description, and executing said logic synthesis tool scripts to synthesize the RTL code. The step of generating logic synthesis tool scripts comprises the substeps of identifying hardware elements and structure of the IC design, determining interrelationships between said identified hardware elements and structures, and generating logic synthesis tool scripts to synthesize said identified hardware elements to netlists as a function of said hardware elements and said interrelationships.Type: GrantFiled: February 20, 1998Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventor: Guy Dupenloup
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Patent number: 6289386Abstract: A network interface unit which implements a low latency algorithm for buffer credit calculation. In one embodiment, a system network is provided with a remote node coupled to a local node by a serial communications link. The remote node is configured to transmit a data frame to the local node only if the remote node receives a buffer credit which indicates that the local node has available receive buffer space for a data frame. The local node includes a network interface unit for coupling to the serial communications link, and the network interface unit includes a receive buffer, a receive controller, a transmit controller, and a buffer credit manager. The receive controller stores incoming data frames in the receive buffer until they can be forwarded to the i/o bus of the local node. The transmit controller is configured to send buffer credits to the remote node in response to a credit signal from the buffer credit manager.Type: GrantFiled: May 11, 1998Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventor: Rene Vangemert
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Patent number: 6287987Abstract: A method and apparatus for forming a dielectric layer. A dielectric precursor solution is deposited onto a surface of a substrate. The substrate is spun to spread the dielectric precursor solution over the surface of the substrate. A catalyst is introduced through a filter, wherein the filter causes a substantially homogenous distribution of the catalyst within the substrate, wherein a dielectric layer forms containing pores and wherein a solvent is contained in the pores. The solution is dried to form the dielectric layer using a carrier gas after introducing the catalyst, wherein the carrier gas places a positive pressure within the pores while removing the solvent to form a low-k dielectric layer.Type: GrantFiled: April 30, 1999Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventors: Gayle W. Miller, Gail D. Shelton
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Patent number: 6288656Abstract: A receive deserializer which regenerates parellel data words that have been broken into smaller data words and serially transmitted over multiple data channels uses an external state machine to shift word clocks with respect to data until the output of the channel last to receive a predefined data reference pattern is framed and provides storage to hold data for the channels which receive the reference pattern earlier.Type: GrantFiled: December 21, 1999Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventor: Chintan Desai
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Patent number: 6289053Abstract: A system and method for performing motion compensation in an MPEG video decoder. The system comprises a horizontal half pixel compensation arrangement including multiple adders and multiplexers which perform horizontal half pixel compensation using an addition function, a division function, and a modulo function on pixel data. The system also includes a register bank which provides the ability to store an array of reference data when vertical half pixel compensation is required. The system also includes a verical half pixel compensation arrangement, which also includes multiple adders and multiplexers which perform vertical half pixel compensation using an addition function, a division function, and a modulo function on pixel data. Reference data and odd pixel data is transferred into and within the system in a predetermined arrangement. Reference and odd pel data may comprise either luma or chroma data.Type: GrantFiled: July 31, 1997Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventors: Surya P. Varanasi, Satish Soman
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Patent number: 6288453Abstract: A single multifunctional structure can be used to determine the alignment accuracy of the contact layer and the interconnect layer by inline visual inspection and by determination of the end of line electrical resistance properties.Type: GrantFiled: September 13, 1999Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventor: Victer Chan
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Patent number: 6289491Abstract: A method of determining circuit characteristics of an integrated circuit design as defined by a generic netlist comprising the steps of identifying hardware elements in the generic netlist, determining key characteristics for each of said identified hardware elements, determining interconnections of said identified hardware elements, and detecting the degree of conformity of said identified hardware elements, said key characteristics, and said interconnections to predetermined configurations. The systems further identifies all cells in the generic netlist, determines for each cell the type of cell, accumulates cell types and cell type counts, and notifies an operator of said accumulated values.Type: GrantFiled: February 20, 1998Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventor: Guy Dupenloup
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Patent number: 6288773Abstract: A method of exposing an alignment mark defined in a first side of a semiconductor wafer includes the step of engaging a second side of the wafer with a wafer chuck. The method also includes the step of positioning the wafer in a chamber having a photochemical reactant gas present therein during the engaging step. Moreover, the method includes the step of impinging laser beams on the first side of the wafer such that a reactant specie is generated from the photochemical reactant gas. Yet further, the method includes the step of removing material from the first side of the wafer with the reactant specie. An apparatus for exposing an alignment mark defined in a first side of a semiconductor wafer is also disclosed.Type: GrantFiled: December 11, 1998Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventors: Gregory A. Johnson, Kunal N. Taravade
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Patent number: 6288598Abstract: A fuse circuit that includes a fuse and a full latch connected to the fuse. The fuse circuit is configured to receive a plurality of input signals including a preset signal and an enable signal. Preferably, a first pass gate is connected to the fuse and to the full latch and is configured to receive the enable signal and a second pass gate is connected to the full latch and is configured to receive the preset signal. Preferably, an output signal line is connected to the full latch and is configured to carry the output signal. The fuse circuit is configured to set the fuse using the preset signal. Ideally, the fuse circuit is configured to provide no direct path between VDD and VSS while using the preset signal to set the fuse. The fuse circuit is configured to provide an output signal which is dependent on the status of the fuse and the state of the enable signal.Type: GrantFiled: November 2, 2000Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventors: Johnnie Huang, Ghasi Agrawal
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Patent number: 6289495Abstract: A method for routing nets in an integrated circuit design, said method comprising the steps of forming a routing graph for an integrated circuit design, said routing graph have edges in a first direction and edges in a second direction, globally routing said integrated circuit design in accordance with said routing graph, dividing the routing graph into strips, for each strip in the routing graph, generating a general task for optimizing the routing in the strip, solving general tasks in parallel by assigning different processors different strips to process.Type: GrantFiled: April 17, 1998Date of Patent: September 11, 2001Assignee: LSI Logic CorporationInventors: Pedja Raspopovic, Ranko Scepanovic, Alexander E. Andreev
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Patent number: 6285077Abstract: A package for an integrated circuit is disclosed. The package comprises two layers (a top layer and a bottom layer) of flexible tape, each of which has a top surface and a bottom surface, with metal traces on the top surface. A die is mounted on top of the two layers and wire bonds connect bond pads on the die to metal traces on each of the two flexible tapes. The metal traces are routed along the top surfaces of the flexible tapes and are coupled to solder balls through holes in the tapes. These solder balls are mounted along the bottom of the package and serve as the electrical interface to a printed circuit board. Additional holes in the bottom layer tape allow solder balls to extend through the bottom layer tape so that they may be electrically coupled to traces on the top layer tape.Type: GrantFiled: August 19, 1999Date of Patent: September 4, 2001Assignee: LSI Logic CorporationInventors: Chok J. Chia, Seng-Sooi Allen Lim, Qwai Hoong Low
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Patent number: 6285263Abstract: A voltage controlled oscillator (VCO) having a generally linear transfer characteristic across a wide frequency range of operation. The VCO is comprised of a voltage-to-current converter (V-I) and a current-controlled oscillator (ICO). A linearization of the output response of the VCO is accomplished by proper selection of the output responses of the V-I and ICO circuits, where the V-I portion is designed to have an inverse nonlinearity response as compared to the nonlinearity response of the ICO portion of the VCO. The combined effect is a linear response for the VCO. A nonlinear V-I characteristic can be achieved by adding several piecewise linear responses together to produce a combined nonlinear response.Type: GrantFiled: April 21, 1998Date of Patent: September 4, 2001Assignee: LSI Logic CorporationInventor: Michael B. Anderson
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Patent number: 6285035Abstract: An apparatus for polishing a first side of a semiconductor wafer down to a desired level includes a polishing platen having a polishing surface. The apparatus also includes a wafer carrier having a first sub-carrier and a second sub-carrier which is concentric to the first sub-carrier. The first sub-carrier is configured to engage a first radial portion of the wafer by a second side of the wafer and apply first pressure to the first radial portion in order to press the first radial portion against the polishing surface of the polishing platen. The second sub-carrier is configured to engage a second radial portion of the wafer by the second side of the wafer and apply second pressure to the second radial portion in order to press the second radial portion against the polishing surface of the polishing platen.Type: GrantFiled: July 8, 1998Date of Patent: September 4, 2001Assignee: LSI Logic CorporationInventor: Kunal N. Taravade
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Patent number: 6285637Abstract: A method and apparatus for automatically identifying the format of a sector in an optical storage device. Information on an optical disc is separated into data and subcode streams. The type of optical data is identified, and a first signal is generated to represent the type. Next, if the type is CD-ROM, the mode is identified, and a second signal is generated to represent the mode. Thirdly, if the mode is Mode-2 CD-ROM, the form is identified, and a third signal is generated to represent the form. A single signal may also be used to represent the type, mode, and form. In a CD embodiment, the type is identified by polling a type indicator bit, the mode is identified by polling the mode indicator bits, and the form is identified by comparing a first set of subheader bytes to a second set of subheader bytes, and polling a form indicator bit.Type: GrantFiled: December 11, 1998Date of Patent: September 4, 2001Assignee: LSI Logic CorporationInventors: Venitha L. Manter, David A. Fechser