Abstract: In a frequency control arrangement 200 of the type comprising an oscillator 270, a mark or space counter 210, a frequency detector 220 and an error signal calculator 230-260, 290 and in which it is desired to control the oscillator 270 to resonate at a frequency substantially equal to the frequency of a received data stream, the oscillator 270 is implemented as a four phase ring oscillator (FIG. 1, ref 110) arranged to provide phased clock signals to the mark or space counter (FIG. 1, ref 100). This allows the mark or space counter to be arranged to measure the length of the marks or spaces of the data with increased resolution.

Abstract: A method for optimizing bus transactions in a data processing system is provided. A bus transaction optimizer receives an original bus transaction request which includes an original start address of a target memory for the original bus transaction, an original byte size for a number of bytes for the original bus transaction, and an original bus command for the original bus transaction. The bus transaction optimizer generates multiple bus transaction requests in response to a determination that the original byte size is greater than or equal to a predetermined multiple transfer byte size data value. The multiple bus transaction requests may include at least one high-performance bus transaction request and at least one low-performance bus transaction request.

Abstract: A backside failure analysis capable integrated circuit package having a removable plug for exposing the backside of the die or a cavity on the backside of the package for exposing the backside of the die. The package uses either a standard lead frame which must be removed prior to conducting a backside failure analysis or a non-standard lead frame which provides for access to the back side of the die.

Abstract: An aerial image produced by a mask having transmissive portions is simulated by dividing the transmissive portions of the mask into primitive elements, obtaining a response for each of the primitive elements, and then simulating the aerial image by combining the responses over all of the primitive elements.

Abstract: A phase-locked loop (PLL) is provided, which includes a PLL reference input, a PLL output and a phase detection loop coupled between the PLL reference input and the PLL output. The phase detection loop has a loop filter node. A delay element is coupled within the phase detection loop and has a variable delay, which can be increased to a critical delay at which the phase detection loop becomes unstable. A demodulator is coupled to the loop filter node and is adapted to demodulate a modulated voltage on the loop filter node. The demodulator has a demodulated output, which is representative of a phase margin of the phase detection loop when the delay element has the critical delay.

Abstract: A confinement device for operative arrangement within a substrate etching chamber, having a lower surface of the device generally arranged over a substrate outer top surface such that a gap-spacing therebetween is generally equidistant. This spacing is less than a sheath thickness for the plasma, preferably less than ⅓rd of an inner width of an aperture through the lower surface of the device. The aperture, sized preferably greater than 3 times the sheath thickness, is in communication with a channel of the device in which an etchant gas can be confined for reaction to selectively etch a localized area in the substrate outer top surface generally below the aperture. A system for dry etching an IC wafer includes a substrate etching chamber and a confinement device. The etchant gas may be a plasma induced and sustained by RF energy, a microwave source, or other source, as designed.

Abstract: A method of translating an integrated circuit chip (IC) design as represented by RTL code to generic netlist using a logic synthesis tool comprising the steps of parsing the RTL code using analyze command of the logic synthesis tool, building the generic netlist using evaluate command of the logic synthesis tool, and recording the generic netlist to a dump file outside the logic synthesis tool. The dump file comprises characteristics of each input ports of current design, characteristics of each output ports of the current design, and characteristics of each cells of the current design.

Abstract: A method and apparatus for providing a constant output power supply that is different from a system power supply. A system power supply voltage is sensed and compared to a predetermined output voltage value. If the supply voltage is greater than the voltage value, the supply voltage is decreased, such as through regulation. If the supply voltage is less than the votlage value, the supply voltage is increased, such as through charge pumping. The apparatus is preferably coupled between a system power supply and a circuit that operates on a voltage that is different from the supply voltage.

Abstract: A method and apparatus for configuring a sector map in an optical storage device. Format identification information is used to generate a sector format word. The sector format word is stored in a sector map in buffer memory. Upon receiving a data retrieval request from a host, the sector format word is decoded, and the data field size is adjusted to conform with the format information contained in the decoded sector format word.

Abstract: An apparatus and method for manufacturing a device using lithography. An underlayer is deposited on a first surface, the underlayer of which is composed of a first resist material adapted to be substantially free of photoacid generators and which includes an acid labile polymer group. A topcoat layer is deposited on top of the underlayer which is composed of a second resist material adapted to be substantially free of acid labile polymer groups and including a photoacid generator. Upon exposure of a portion of the topcoat layer to radiation through to form an exposed region and an unexposed region of a lithographic pattern, photoacid is generated by the topcoat layer and delivered to an interface between the underlayer and the topcoat layer such that the generated photoacid at the exposed region deprotects the acid labile polymer groups at the underlayer top surface to form a deprotected region and a protected region.

Abstract: A method and apparatus in a data processing system for multiple bus arbitration, wherein the data processing system includes a first bus connected to a second bus by a bridge. In response to receiving a request for a target device from a master device connected to a first bus, a determination is made as to whether the target device is connected to the first bus. The bridge is selected in response to determining that the target device is located on the second bus. The bridge initiates a request for the second bus in response to the selection of the bridge. The first bus and the second bus are connected to each other by the bridge in response to the bridge receiving a grant to the second bus, wherein the master device transfers data between the master device and the target device across the bridge.

Abstract: Nets are routed on an integrated circuit device by dividing a portion of the integrated circuit device into a first group of tiles. A first routing graph is then formed as a function of the first group of tiles and nets are routed as a function of the first routing graph. A new group of tiles is formed by dividing the tiles of the first group of tiles, a new routing graph is formed as a function of the new group of tiles, and nets are rerouted as a function of the new routing graph. The steps of the preceding sentence are then repeated and each time a new group of tiles is formed, the tiles are divided in a same first dimension, resulting in tiles have progressively smaller lengths in that first dimension, while the size of the tiles in a second dimension does not change.

Abstract: A method and apparatus are provided for addressing a sequence of orderly spaced memory locations of a computer system, without requiring the address of each memory location to be retrieved from a register of the computer system. This is accomplished by storing at least part of the sequence into a cache memory of the computer system during a first operation referencing a first memory location within the sequence, detecting that a second operation references a second memory location within the sequence and retrieving the contents of the second memory location from the cache memory in parallel with calculating the memory address of the second memory location.

Abstract: Provided are a self-aligned semiconductor fuse structure, a method of making such a fuse structure, and apparatuses incorporating such a fuse structure. The fuse break point, that point at which the electrical link of which the fuse is part is severed by a laser beam, is self-aligned by the use of photolithographically patterned dielectric and a heat sink material. The self-alignment allows the size and location of the break point to be more forgiving of the laser beam size and alignment. This has several advantages, including allowing photolithographic control and effective size reduction of the laser spot irradiating the fuse material and surrounding structure. This permits reduced fuse pitch, increasing density and the efficiency of use of chip area, and results in reduced thermal exposure, which causes less damage to chip. In addition, laser alignment is less critical and therefore less time-consuming, which increases throughput in fabrication.

Abstract: An apparatus for planarizing a semiconductor wafer having a polishing endpoint layer that includes a catalyst material is disclosed. The apparatus is operable to detect the endpoint based upon the chemical slurry whether a catalytic reaction has occurred due to the polishing platen removing a portion of the catalyst material from the wafer.

Abstract: A method of designing an integrated circuit including at least one predefined core module and a custom logic circuit whereby clock skew between the core module and the custom logic circuit may be reduced. An integrated circuit designer selects core modules having desired functionality for inclusion within an integrated circuit from a library of core modules. Each core module in the library is predefined and pre-verified and may be provided as a synthesizeable register-transfer level (RTL) description which can be synthesized along with RTL descriptions of other logic blocks in the integrated circuit. Alternatively, each core module may be provided as a pre-laidout integrated circuit mask which can be included in the final integrated circuit mask design. Upon selection of appropriate core modules, the designer defines a custom logic circuit for integration with the core modules.

Abstract: A precision delay circuit having two delay chains to provide equal delay periods is described. A rising edge of an input pulse signal is supplied to the first delay chain and the falling edge is supplied to the second delay chain. The resultant output signal maintains the pulse width of the input signal and pulse distortion is minimized. In another aspect, a delay circuit for generating a delayed assertion signal that does not maintain the width of the original input signal pulse and which is substantially immune to noise problems is described. An assertion edge of a resultant pulse is timed by the incoming pulse, but the de-assertion edge is timed by the delayed de-assertion edge of the incoming pulse.

Abstract: A polishing pad surface having a surface designed for chemical mechanical polishing of a substrate surface is described. The polishing pad surface includes a first area on the surface exposed to and capable of contacting a first amount of the substrate surface during chemical-mechanical polishing and a second area on the surface exposed to and capable of contacting a second amount of the substrate surface during chemical-mechanical polishing, wherein the second amount is larger than the first amount of the substrate surface to produce a more uniformly polished substrate surface.

Abstract: An integrated circuit device is disclosed having a BIST Uinit with recolfiLgurable data retention testing for a memory array. In one embodiment, the integrated circuit device includes a memory array, a BIST unit, an externally-programmable pause count register, and a pause counter. The BIST unit is configured to apply a test pattern of memory accesses to the memory array. The test pattern preferably includes a first phase for writing data values to the memory array, a second phase for stressing the memory array, and a third phase for verifying the data values after the array has been stressed. The length of the second phase is determined by the count stored in the externally-programmable register. The count may be loaded into the pause counter by the BIST prior to the second phase. In the second phase, the BIST unit asserts a pause signal which causes the pause counter to suppress the clock signal to the BIST unit during the second phase, thereby suspending the BIST unit's activity.

Abstract: Adaptive clock recovery enables the clock of a CBR service to be recovered, this service being emulated from an ATM transmitter, is provided at an ATM receiver. The fill level of a first buffer receiving a stream of cells is used to provide coarse control of the rate of output of a stream of cells from the first buffer. The fill level of a further, fine, buffer receiving said stream of cells from the first buffer is monitored for determining a clock frequency, corresponding to the service clock frequency, for outputting cells from the fine buffer. The first buffer fill level control provides low pass cell jitter filtering by selectively supplying a first or a second clock frequency for outputting cells from the first buffer. The fine filter fill level control employs a phase locked loop responsive to the current fill level to set a clock frequency for reading out said fine buffer at the service clock frequency.