Abstract: The present invention relates to a semiconductor device, preferably a capacitor, and a method of forming the same. The method adds only a single additional masking step to the the fabrication process and reduces problems relating to alignment of various layers. A relatively thick insulation layer is formed over a bottom electrode. An opening having a sidewall that is etched in the insulation layer using a mask to expose a portion of the bottom electrode. Once the mask is removed, a dielectric layer and conductive layer are then sequentially deposited over the entire structure, including sidewalls. Thereafter, chemical-mechanical polishing is used to remove portions of the conductive layer and the dielectric layer so that the conductive layer and dielectric layer which remains forms, for example, the top electrode and dielectric layer of the integrated circuit capacitor.

Abstract: A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be coupled to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.

Abstract: A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated circuit layout design with a design rule checker to locate features of the integrated circuit layout design meeting predefined criteria; and (b) performing optical proximity correction on the features meeting the criteria in order to generate a reticle design. The criteria employed by the design rule checker to select features include outside corners on patterns, inside corners on features, feature size, feature shape, and feature angles.

Abstract: A method and a circuit are described for generating a frequency signal having fine frequency control, and which are suitable for implementation on an-integrated circuit. The output frequency is generated having a controllable relationship with an oscillator frequency by using multiple phases of the oscillator signal. The output is provided by selecting a signal from the plurality of phases, and the frequency control is achieved by varying the selection cyclically, so that the output signal may be composed of segments of different phases. The cyclic selection is performed at a controllable rate to achieve stable generation of an original frequency signal.

Abstract: A capacitor is fabricated on a semiconductor substrate by first forming a first capacitor electrode on the semiconductor substrate and forming a planar insulating layer over the first capacitor electrode. A photoresist layer is then formed over the planar insulating layer and patterned utilizing in only masking step to form an opening over the first capacitor electrode. Through the opening, the planar insulating layer is etched, and a capacitor dielectric layer is thereafter formed. A second capacitor electrode is then formed over the capacitor dielectric layer in alignment with the first capacitor electrode. The structure is planarized to expose the planar insulating layer. In a preferred embodiment, a trench in the second capacitor electrode is protected during planarization by a spin-on photoresist that is stripped following planarization.

Abstract: A horizontal deflecting optical waveguide is formed in an integrated circuit-like structure having a substrate and at least one layer of dielectric material above the substrate. A trench is formed in the dielectric material, and the trench has first and second portions angularly joined at a bent portion. A reflective layer of material adjoins, conforms to and extends along the side walls of the trench. A core of optically transmissive material conforms to the reflective layer within the trench. The reflective layer forms a wall at the bent portion which reflects light from the core located in one portion into the core located in the other portion.

Abstract: A fixture for holding an integrated circuit. The integrated circuit is of the type having a front side and an opposing back side. The fixture positions the integrated circuit for simultaneously electrically probing and viewing both the front side and the back side of the integrated circuit. A supporting brace provides a support that is immobile in at least a first direction, against which to cooperatively brace the integrated circuit. A first jaw piece is disposed adjacent the supporting brace. The first jaw piece has a vee shape for receiving a first corner of the integrated circuit and cooperatively aligns the integrated circuit into a position for simultaneously electrically probing and viewing the front side and the back side of the integrated circuit. An adjustable brace provides a movable second position in the first direction relative to the supporting brace, against which to cooperatively brace the integrated circuit with the supporting brace.

Abstract: A system determines the root of a polynomial by employing a parallel structure that implements a Chien Search and minimizes the amount of storage required. The location of an error in a codeword can be derived from the root of an error locator polynomial. The performance of the Chien Search is enhanced by the parallel structure, and the location of the error can be easily determined using a simple calculation that preferably includes the cycle count, the parallelism, and the index of the multiplier/summer rank that indicates a root. Multiple ranks of multipliers receive data stored in a single array of data storage units. Multiplier values of each multiplier are based on the elements of a Galois Field. A method configures data storage units, multipliers, summers, and comparators, and performs a Chien Search. The location of an error in a codeword is determined using a simple calculation based on a determined root of an error locator polynomial.

Abstract: A method of forming a semiconductor device on a substrate including the steps of: forming a first recess in the substrate; depositing an insulator in the first recess so that an isolation region is formed when the first recess is filled with the insulator; forming a second recess in a predetermined area of the substrate; forming a recess insulation layer on the surface of the second recess; depositing a conductive material on the recess insulation layer and in the second recess so that a gate region is formed when the second recess is filled with the conductive material; removing a sufficient amount of the insulator and the conductive material so that the top surfaces of the insulator, the conductive material and the substrate are substantially at the same level.

Abstract: A die including a corrosion monitoring feature is described. The die includes: (i) a surface including an active die region and a scribeline region that is adjacent the active die region; (ii) an insulating layer disposed above the surface and includes a first corrosion sensitive metal plug and a second corrosion sensitive metal plug in the scribeline region; and (iii) a metallization layer positioned above the insulating layer, the first corrosion sensitive metal plug and the second corrosion sensitive metal plug in the scribeline region and the metallization layer disposed above second corrosion sensitive metal plug is patterned to provide the metallization layer with a first opening extending from a top surface of the metallization layer down to a top surface of the second corrosion sensitive metal plug such that a solvent introduced above the top surface of the metallization layer flows into the second corrosion sensitive metal plug disposed below through the first opening in the metallization layer.

Abstract: System and method for reproducing information represented by data (e.g., dynamic image compressed data), stored on a storage medium, in reverse order. Group of pictures (GOP) data sets read from a storage medium are stored in a memory (e.g., a stream buffer). Each GOP data set includes a plurality of pictures sequentially ordered from a first picture to a last picture, and each picture includes corresponding picture data. A given GOP data set is read from the memory multiple times in order to reproduce the pictures of the GOP data set in reverse order. In addition to the memory, one embodiment of the system includes a decoder for decoding picture data, and a memory controller coupled to the memory and the decoder. The memory controller receives a GOP data set read from the storage medium, and stores the GOP data set in the memory. The memory controller initializes a counter by storing a value equal to a total number of the pictures in the GOP data set within the counter.

Abstract: A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a “peek-ahead” FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream.

Abstract: A digital-versatile disk (DVD) playback-controller integrated circuit (IC) writes data to a block in an embedded memory buffer while row syndromes are being generated in parallel. The block has rows and columns. Row syndromes are generated on-the-fly as the data is written from the DVD disk to the memory buffer. Row syndrome generation thus requires no memory access cycles. Column syndrome generation is delayed until row correction is completed. Once errors in the rows identified by the row syndromes are corrected, column syndromes are generated. The bytes received from the DVD disk for the current row are accumulated into intermediate row syndromes. Received bytes are accumulated for the row until all of the row's bytes have been received and accumulated. The final accumulated row syndromes are written to the embedded memory buffer for later row error-correction.

Abstract: The present invention prevents deposition on product wafers of microbubbles generated from chemical solution circulation systems for wet etching or wet cleaning, or pure water supply systems during manufacturing processes of semiconductors or liquid crystals. A separator is provided on the inner wall of a chemical solution bath for etching or cleaning wafers to cover a process solution nozzle. The separator comprises an upper microbubble discharge tube extending upright for discharging microbubbles and lower outlets for horizontally introducing a process solution into the process bath.

Abstract: A modular, scalable system architecture that includes a data traffic master for providing high-bandwidth, shared memory connections to two or more processor units. The system architecture includes an array of memory modules coupled to an array of processor units by a traffic master. Each of the memory modules is connected to the traffic master by a data channel, and each data channel includes an address path and a data path. The data channels all share a common data path bit-width. On the other hand, the processor units are each coupled to the traffic master by data busses that have address and data path widths dictated by their design. Although the address path width of a given processor unit may be unable to span the address space of the shared memory, the processor unit can nonetheless access any memory location through the use of page pointers.

Abstract: A method of fabricating a semiconductor wafer includes the step of fabricating a number of die on the wafer. The method also includes the step of fabricating a memory device on the wafer. The method further includes the step of testing the number of die with a die testing apparatus so as to obtain test data associated with the number of die. In addition, the method includes the step of storing the test data obtained during the testing step in the memory device. Moreover, the method includes the step of retrieving the test data from the memory device. Yet further, the method includes the step of operating a packaging apparatus so as to package a first die of the number of die based on the test data. A semiconductor wafer is also disclosed.

Abstract: Integrated circuit chip design in which a technology-independent description of an integrated circuit design is obtained. A first component is selected from a pre-defined first library based on the technology-independent description, and an interconnection is specified between the first component and a second component based on the technology-independent description. The first component and the second component are laid out on a surface of the integrated circuit chip so as to obtain an initial layout, and a routing characteristic for the interconnection is estimated based on the initial layout. The first component is then replaced with a new component selected from a pre-defined second library based on the routing characteristic. According to this aspect of the invention, the pre-defined first library is smaller than the pre-defined second library.

Abstract: A DC drift canceller circuit is disclosed. The circuit includes a decision device including an input and an output and a first adder configured to received the input and the output of the decision device. The first adder produces an error signal indicative of the difference between the input and output of the decision device. A noise filter of the circuit is configured to receive the error signal. A second adder of the circuit includes a first input coupled to the input of the canceller circuit and a second input coupled to the output of the noise filter such that the output of the second adder is substantially free of any DC drift component of the input signal. The output of the second adder is coupled to the input of the decision device. In one embodiment, the decision device comprises a slicer. In one embodiment, the noise filter comprises a low pass filter.

Abstract: A system and method for compensating for a voltage offset between an inverting input and a noninverting input of an op amp to provide a stable bandgap reference. The method including measuring the voltage offset between the inverting input and the noninverting input of the op amp and searching for a compensating current input to the op amp that compensates for the voltage offset. A programmable current source is set to output the compensating current to the op amp.

Abstract: A method and apparatus for controlling amplifier operating angle provides a corresponding increase in amplifier efficiency through a continual adjustment of operating angle from Class A, through Class AB, to Class B, an improved bandwidth in the output stage by preventing the output stage from reaching cutoff and the ability to adjust the high frequency content of the drive waveform to match that of the output stage thereby attaining the highest efficiency consistent with required distortion levels. A push-pull amplifier is coupled to a differential pushpull current drive source with out of phase drive signals and a preprocessing circuit with a first set of current sources which mirror one drive signal and a second set of current sources which mirror the other drive signal.