Abstract: A preconditioning mechanism for preconditioning a polishing pad is described. The preconditioning mechanism includes an arm capable of being disposed over the polishing pad and a head section located on a distal end of the arm and rotatable about a central axis. Furthermore, the head section includes at least two heads oriented about the central axis and have surfaces for either conditioning or preconditioning the polishing pad, whereby rotation of the head section about the central axis by defined amounts presents at least two heads to the polishing pad so that different of the two heads can engage the polishing pad for conditioning or preconditioning depending upon how far rotation has proceeded.

Abstract: Methods and structures for defining partitions within a RAID storage system LUN such that each partition is managed in accordance with RAID management techniques independent of the other partitions. The total data storage of the LUN is subdivided and mapped into a plurality of partitions also referred to as partitions. Initially, each partition is configured and mapped to run as a RAID level 1 mirrored storage area. As performance and storage capacity needs as measured for each partition dictate, a partition of a LUN may be reconfigured to use a different RAID level (i.e., level 3 or 5) to reduce overhead storage needs at the cost of decreased write performance. A partition may later be returned to RAID level 1 as performance needs so indicate. Each partition is therefore managed in accordance with its own RAID level of management.

Abstract: A video filter processes pixel data by storing multiple lines of pixel data in a memory buffer and computes a weighted average of the data using a plurality of multipliers and accumulators. The pixel data which, for example, may represent luminance and/or chrominance values is stored in the buffer in an interleaved fashion. Preferably multiple lines of pixel data is stored in a single buffer, thereby reducing the number of traces that would otherwise be required if a separate buffer was used for each line of pixel data.

Abstract: A photolithography apparatus for deep UV enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. this photolithography apparatus employs a different approach to contrast enhancement which is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: A system and method for a supply-independent VCO biasing scheme for generating bias voltages and currents for a VCO of a phase-locked loop are disclosed A biasing scheme for generating a bias electrical signal comprises a first and second current source coupled to a power supply, a current drain coupled to the second current source and to ground, a replica device having a first node, a second node coupled to the second current source and the current drain, and a third node coupled to ground, and a first and second current splitting device having first nodes coupled to each other and to the current source and having third nodes coupled to the first and second nodes of the replica device, respectively.

Abstract: An audio decoder architecture makes use of various component sharing techniques to conserve hardware and reduce implementation cost. In one embodiment, the audio decoder comprises a bitstreamer, a synchronization controller, a first and second decode controllers, a memory module, a data path, and an output buffer. The bitstreamer retrieves compressed data and provides token-aligned data to the synchronization controller and decode controllers. The synchronization controller initially controls the bitstreamer to locate and parse audio frame headers to extract decoding parameters. The synchronization controller initiates the decode controller which corresponds to an identified compression format, and turns control of the bitstreamer and data path over to the selected decode controller. The selected decode controller then controls the bitstreamer to parse the variable length code compressed transform coefficients.

Abstract: A novel device which efficiently decodes data encoded with a cyclic code in communications systems where a convolutional code is applied after the cyclic code during encoding. Specifically, the device accepts data provided in time reversed order by a Viterbi decoder which decodes the convolutional code. In a preferred version, the device employs linear feedback shift registers with multiple feedback paths. A set of multipliers corresponding to a set of coefficients is interposed in the feedback paths such that when data is shifted through the feedback shift registers, the device performs division by x for an input bit equal to 0, and, for an input bit equal to 1, performs division by x and then adds xk+m−1. The set of multipliers includes a set of weighting multipliers corresponding to coefficients of a weighting polynomial such that addition of xk+m−1 is performed for an input bit equal to 1.

Abstract: A program translates an EDIF netlist that defines a circuit into a data file containing a predetermined subset of the circuit-defining data. The program operates on netlists that define designs and library cells. The data file is useful to describe the circuit, or a portion of the circuit, in a simpler and more intuitive format, so that users unfamiliar with the circuit or with EDIF format can quickly understand the circuit components and connectivity. The subset of circuit data is parsed out of the EDIF netlist and stored in the data file. The data file is useful for extracting and clearly describing the instances connected to a specified signal. The data file is also useful for generating a graphical or textual display of the circuit. A user may specify primary ports, signals, global ports, and cell instances to focus the subset of circuit data on the portion of the circuit of interest. Signals may be traced on a graphical display. Another program can create an EDIF netlist from the data file.

Abstract: A low voltage bipolar transconductor circuit with extended dynamic range is disclosed. The transconductance circuit provides a differential current output signal and generally comprises a first and a second differential pair of transistors coupled to a differential input signal and to a load, and having transistors area ratios of 1:r and r:1, respectively. The transconductance circuit further comprises at least one first pair of diodes having positive nodes coupled to each other and to the load, negative nodes coupled to the first differential transistors, and a diode area ratio of r:1, and a least one second pair of diodes having positive nodes coupled to each other and to the load, negative nodes coupled to the second differential transistors, and having a diode area ratio of 1:r.

Abstract: Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes a plurality of correction values that are used to correct a plurality of features of the layout design that have a selected space dimension. Identifying each of the plurality of features that have the selected space dimension. The method further includes correcting each of the plurality of features that have the selected space dimension with one correction value of the plurality of correction values of the run set. Preferably, the run set is generated from a correction table that has the plurality of correction values.

Abstract: A method of fabricating a semiconductor wafer having a polishing endpoint layer which is formed by implanting ions into the wafer includes the step of polishing the wafer in order to remove material from the wafer. The method also includes the step of detecting a first change in friction when material of the ion-implanted polishing endpoint layer begins to be removed during the polishing step. The method further includes the step of detecting a second change in friction when material of the ion-implanted polishing endpoint layer ceases to be removed during the polishing step. Moreover, the method includes the step of terminating the polishing step in response to detection of the second change in friction. An apparatus for polishing a semiconductor wafer down to an ion-implanted polishing endpoint layer in the wafer is also disclosed.

Abstract: A quadrature amplitude modulation (QAM) trellis coded modulation (TCM) decoder for decoding a stream of QAM TCM signals is disclosed. Each of the signals has a plurality of associated branch metrics and has an in-phase component and a quadrature component. The in-phase component is defined by a plurality of in-phase symbols and the quadrature component is defined by a plurality of quadrature symbols. The QAM TCM decoder includes a first Viterbi decoder and a second Viterbi decoder. The first Viterbi decoder is configured to receive an in-phase component of a QAM TCM signal for decoding the associated in-phase symbols into an in-phase decoded bit and a plurality of uncoded in-phase bits. The second Viterbi decoder configured to receive a quadrature component of the QAM TCM signal for decoding the associated quadrature symbols into a quadrature decoded bit and a plurality of uncoded quadrature bits. The first and second Viterbi decoders are adapted to decode 64- or 256-QAM TCM signals.

Abstract: The present invention provides an improved method and apparatus for concurrent execution of operating systems. A software abstraction layer provides an interface that allows a first operating system to run concurrently with a second operating system on the same data processing system, in which the first operating system is in communication with the base machine in the data processing system. Interaction between the second operating system and the base machine is handled by the software abstraction layer translating requests and calls from a format normally made by the second operating system to the base machine into a format that is processed by the first operating system. Request and data intended for the second operating system are received by the first operating system, sent to the software abstraction layer and translated by the software abstraction layer into a format usable by the first operating system.

Abstract: A method for implementing net routing for an integrated circuit design with parallel processors, said method comprising the steps of creating a character array, filling said character array with a first character, dividing a plurality of nets into groups, supplying a plurality of locks and assigning each said group its own individual lock, assigning for each net in said plurality of nets a position in the character array; and placing a second character in the position of a particular net in said character array when the net is operated on by a processor and replacing said second character with the first character after said operation is completed.

Abstract: A predriver for driving an output data buffer at high frequencies includes a data input, a data output, a first voltage pull-up circuit, a first voltage pull-down circuit, a delay circuit and a second voltage pull-down circuit. The first voltage pull-up circuit is coupled to the data output and has a control terminal coupled to the data input. The first voltage pull-down circuit is coupled to the data output and has a control terminal coupled to the data input. The first voltage pull-down circuit, when active, is adapted to at least temporarily hold the data output above a selected voltage. The delay circuit is coupled to the data input. The second voltage pull-down circuit is coupled to the data output and has a control terminal coupled to an output of the delay circuit.

Abstract: A controllable latch/register circuit for an integrated circuit comprises an input latch (30) coupled in series with an output latch (32). The latches are operated under control of a control circuit (34) having mode inputs. In one mode, the latches are operated as a non-transparent register; the output latch (32) holds the output stable while new data is inputted to the input latch (30); the output latch (32) is only opened once the input latch has been latched closed. In one or more other modes, the latches are operated as a single controllable transparent latch; for example, one or the latches (30) can be held permanently open such that operation of the circuit depends entirely on the state of the other latch (32).

Abstract: The present invention includes a charge pump that has an advantageous use in a phase-lock loop. The charge pump includes a current mirror, at least two switches and a loop. The current mirror pumps up loop filters according to input signals. The loop senses the common mode of loop filter nodes and compares them to a reference voltage. If the common mode is not at a desired level, then the loop provides leakage paths that are turned on to bring the nodes to that desired level. The use of the current mirror substantially reduces current mismatch. Furthermore, the loop is active for a relatively short time, thus minimizing the introduction of any errors. The present invention reduces static phase error by reducing current mismatch.

Abstract: A semiconductor package is present along with an associated method. The package comprises a substrate with a top surface and a bottom surface, the substrate having a plurality of electrically conductive vias extending from the top surface of the substrate to the bottom surface of the substrate. A semiconductor device having an active surface, the active surface having a plurality of bonding pads, is attached to the substrate by an adhesive that bas holes that align with the vias. The vias are also aligned with the bonding pads. Solder serves to electrically and mechanically couple each of the bonding pads with a corresponding via. Each of the vias, in turn, is coupled to a solder ball formed on the bottom of the substrate.

Abstract: A system and method for low delay mode operation video decoding embodied in a prefetch buffer and an mbcore including an mbcore pipeline. The mbcore is adapted to check a status of the prefetch buffer at predetermined times and to implement a low delay mode to delay the mbcore pipeline when a data level of the prefetch buffer goes below a threshold at the predetermined times. The mbcore is adapted to ensure that there is a sufficient quantity of data in the prefetch buffer for a particular operation and, in a preferred embodiment, is adapted to check the status of the prefetch buffer at a start of a slice, at a beginning of dct decoding of each coded block. The prefetch buffer and the mbcore operate asynchronously, with the mbcore being adapted to prevent a symbol from splitting between the prefetch buffer and the mbcore.

Abstract: In a frequency control arrangement 200 of the type comprising an oscillator 270, a mark or space counter 210, a frequency detector 220 and an error signal calculator 230-260, 290 and in which it is desired to control the oscillator 270 to resonate at a frequency substantially equal to the frequency of a received data stream, the oscillator 270 is implemented as a four phase ring oscillator (FIG. 1, ref 110) arranged to provide phased clock signals to the mark or space counter (FIG. 1, ref 100). This allows the mark or space counter to be arranged to measure the length of the marks or spaces of the data with increased resolution.