Abstract: An encoded multimedia terminal having a low cost decompression circuit together with a low cost interconnect circuit coupled to a powerful server. The terminal can accept user input via a mouse, keyboard, remote control, or handset. In one embodiment, the server has ports which provide real-time audio and video encoding of source material based on user edits and the original source. An encoded bitstream is then sent to the encoded multimedia terminal for decoding. Broadly speaking, the present invention contemplates an encoded multimedia terminal comprising a microcontroller, a network interface, a multimedia bitstream decoder, and a display controller. The microcontroller receives input from a user-input device and responsively determines a user input signal. The network interface is coupled to the microcontroller to receive the user input signal and is configured to communicate the user input signal to a multitasking server which is executing a software application.

Abstract: A modified chemical-mechanical polishing apparatus is described. The apparatus includes: (i) a polishing pad for providing a surface against which a surface of an integrated circuit substrate is polished during polishing; (ii) an anode on which the polishing pad is secured, the anode including an electrolyzable conductive material; and (iii) a voltage source including a first electrical connection and a second electrical connection, the first electrical connection being connected to the anode and the second electrical connection being configured for connection to the integrated circuit substrate undergoing polishing such that when a voltage is applied from the voltage source in the presence of slurry admixed with an electrolyte composition on the polishing pad, an electrolytic cell results in which the conductive material deposits on the surface of the integrated circuit substrate.

Abstract: An apparatus is provided for conditioning a polishing pad used for chemical-mechanical polishing. The apparatus comprises the retainer ring used to retain the semiconductor wafer against the polishing pad. Accordingly, the retainer ring serves a dual purpose: to retain the wafer in proper CMP position as well as condition the polishing surface while polishing of the wafer. The retainer ring includes an inner surface defining an opening to receive the semiconductor wafer. Dimensioned radially outside the inner surface is an outer surface. Placed on the distal ends between the inner and outer surfaces is an abrasive surface. The abrasive surface extends along a plane parallel to the retained frontside surface of the wafer. Both the wafer and the abrasive surface contact the polishing surface either in a rotation about a stationary axis or orbital movement about that axis.

Abstract: An MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes motion compensation logic which analyzes motion vectors in an encoded frame of the MPEG stream and uses prior decoded reference blocks to recreate the data encoded by the motion vector. The MPEG decoder stores reference block data according to a novel skewed tile arrangement to minimize the maximum number of page crossings required in retrieving this data from the memory.

Abstract: A serial network interface unit which uses indirect addressing to access an exchange table. In one embodiment, the serial network interface unit comprises a serial communications transceiver, a transmit controller, a receive controller, and a register file for storing an exchange table and an index table. The exchange table has slots for storing information about data exchanges, and the index table has an entry for each ongoing exchange to indicate which of the slots is storing information about the exchange. The transmit and receive controllers are coupled to the register file to reference the index table to determine an exchange table slot corresponding to a current exchange and to thereafter update information in the current exchange table slot. A processor may be coupled to the register file via an i/o bus to store inactive (but ongoing) data exchange information to system memory and to replace the inactive data exchange information with information for active data exchanges.

Abstract: A microelectronic integrated circuit includes a semiconductor substrate, and a plurality of CMOS microelectronic devices formed on the substrate. Each device includes a hexagonal ANY element of a first conductivity type (PMOS or NMOS), and a hexagonal ALL element of a second conductivity type (NMOS or PMOS), the ANY and ALL elements each having a plurality of inputs and an output that are electrically interconnected respectively. The ANY element is basically an OR element, and the ALL element is basically an AND element. However, the power supply connections and the selection of conductivity type (NMOS or PMOS) for the ANY and ALL elements can be varied to provide the device as having a desired NAND, AND, NOR or OR configuration, in which the ANY element acts as a pull-up and the ALL element acts as a pull-down, or vice-versa.

Abstract: A tri-state input-output (I/O) buffer which includes a core terminal, a pad terminal and an enable terminal. A pad pull-down transistor and pad pull-up transistor are coupled to the pad terminal and have pull-up and pull-down control terminals, respectively. A pull-down control circuit is coupled between the core terminal and the pull-down control terminal. A pull-up control circuit is coupled between the core terminal and the pull-up control terminal. A feedback circuit is coupled between the pad terminal and the pull-up control terminal for sensing a first voltage on the pad terminal and adjusting a second voltage on the pull-up control terminal based on the sensed first voltage to reduce leakage current through the pull-up transistor when an enable signal received on the enable terminal is an inactive state.

Abstract: A method and apparatus for equalizing the frequency response of a transmission line is provided. The method includes the steps of modelling the frequency response of the transmission media for a predetermined frequency range to a predetermined accuracy; determining a desired equalizer response by taking an inverse of the modelled frequency response of the first step; implementing an equalizer that exhibits the desired response; and utilizing the equalizer to equalize the frequency response of the transmission line. The apparatus includes an adaptive equalizer circuit which includes a plurality of signal processor circuits which each take an input signal from the transmission line and process it to mimic a term in a transfer function which represents an inverse of the transfer function of the transmission line. The signals from these processors are then summed and multiplied by a programmable gain term. Then the input is added to the output of the multiplier to form an output equalizer signal.

Abstract: A clock delay circuit which creates control signals relative to a clock signal which vary in relation to inherent variables arising from manufacturing process, temperature and voltage influences on a memory array. The clock delay circuit preferably comprises a pair of spare word lines and a pair of spare bit lines of the memory, each of which extends across the memory array. Signals conducted along the spare word and bit line create a signal which is supplied to a counter and decoder to supply a plurality of control signals having a timing relationship established relative to the clock. The spare word line and spare bit line comprise electrical characteristics affecting signal propagation time similar to a signal propagation time along one of an actual word line or actual bit line, respectively.

Abstract: A wireless communication device may take the form of a cellular telephone, of a portable personal communication device, or even of a desk top personal computer which is equipped to communicate over the wireless cellular communication system in effect in a particular area. The wireless communication device is configured to self-adapt to various operating frequencies and communication protocols which may be present in the cellular communication environment so that the device is able to provide communications in several service areas even though the frequencies of operation and the communication protocols in use in the service areas may be incompatible with one another. The wireless communication device may also include facilities for transmitting and receiving video, graphics, and data files over an RF bandwidth.

Abstract: Provided is a multi-piece integrated heat spreader/stiffener assembly which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener assembly has two pieces, both composed of a high modulus, high thermal conductivity material shaped to attach to each other and a die on the surface of a packaging substrate. A first piece of this assembly is bonded to the substrate surface adjacent to an electrically connected die and to the top surface of the die prior to the dispensation and curing of underfill material which provides the mechanical connection between the die and the substrate. With the first piece of the assembly in place, access may still be had to at least one edge of the die to dispense and cure the underfill epoxy.

Abstract: A method and apparatus for processing interrupts for a plurality of components connected to and sharing an interrupt line in a data processing system in which interrupts are level sensitive interrupts. The components are connected to the interrupt line by interrupt connections, such as a pin. An interrupt is detected when the interrupt line is in a first state, while an interrupt is absent when the interrupt line is in a second state. Other interrupts cannot be processed while the interrupt line is in a first state. In response to detecting one or more interrupts, the connection associated with the component, for which one or more interrupts are generated, is disabled until all of the interrupts are processed. Disabling the interrupt connection allows the interrupt line to return to the first state and for additional interrupts for other components connected to the interrupt line to be detected and processed.

Abstract: The present invention provides for ESD protection while allowing the use of an input signal that is higher than V.sub.DD. The present invention preferably includes a protection device and a delay circuit coupled to an input pad and to a ground reference. The protection device is a preferred silicon controlled rectifier, and the delay circuit is preferably a low pass filter RC circuit that includes a resistor and a capacitor. A node associated with the delay circuit is coupled to circuitry of an integrated circuit. The circuitry has associated therewith at least one gate oxide breakdown voltage. A gate oxide breakdown voltage is prevented from being applied to the circuitry of the integrated circuit. When an ESD voltage is applied to the input pad, the voltage at that pad ramps or increases quickly. The delay circuit prevents the node from ramping as quickly by delaying the ramping or increasing of the node voltage. This delay provides time for the protection device to turn on and sink the ESD current.

Abstract: A semiconductor package (110) includes a tape substrate (135) having a top surface, a bottom surface, a plurality of conductive metal traces (115) formed on the top surface and a plurality of holes (130) arraigned in an array pattern formed through the tape substrate (135) exposing the conductive traces (115) from the bottom surface. A nonconductive metal plate or stiffener frame (155) attached to the bottom surface of the tape substrate (135) to support the tape substrate (135) during assembly. The stiffener frame (155) having through holes (160) corresponding to the holes (130) in the tape substrate (135) and being made from anodized aluminum, thus making it electrically nonconductive. An integrated circuit (IC) chip (120) is mounted on the top surface, opposite the stiffener frame (155).

Abstract: The present invention addresses the problem of describing an arbitrary object (up to user-defined limits) given a set of triangles with vertex normals describing the object. A novel method of successively merging traingles into larger and larger patches to compute a set of "as-few-as-possible" Bezier patches is presented. This method is not only applicable to arbitrary objects, but also aims at producing as few patches as possible depending on the geometry of the input object. Also presented are methods to enforce C.sup.0 - and C.sup.1 -continuity between a pair of patches B.sub.L (s,t) and B.sub.R (s,t), placed arbitrarily. The methods perturb the appropnate control points to achieve geometric continuities. For C.sup.0 -continuity the area of the hole between the patches is minimized by formulating the area as a series of linear programs, where the continuity has to be enforced across the adjacent boundary curves B.sub.L (1,t) and B.sub.R (0,t). Similarly, to enforce C.sup.

Abstract: A method and apparatus for equalizing the frequency response of a transmission line is provided. The method includes the steps of modelling the frequency response of the transmission media for a predetermined frequency range to a predetermined accuracy; determining a desired equalizer response by taking an inverse of the modelled frequency response of the first step; implementing an equalizer that exhibits the desired response; and utilizing the equalizer to equalize the frequency response of the transmission line. The apparatus includes an adaptive equalizer circuit which includes a plurality of signal processor circuits which each take an input signal from the transmission line and process it to mimic a term in a transfer function which represents an inverse of the transfer function of the transmission line. The signals from these processors are then summed and multiplied by a programmable gain term. Then the input is added to the output of the multiplier to form an output equalizer signal.

Abstract: Integrated circuit chips (IC's) require proper placement of many cells (groups of circuit components) and complex routing of wires to connect the pins of the cells. Designing of the IC's require meeting real-world constraints such as minimization of the circuit area, minimization of wire length within the circuit, and minimization of the time the IC requires to perform its function, referred to as the IC delay. Because of the large number of cells and nets of an IC, the process of determining IC delay of an IC design requires a lot of time. The present invention discloses a method and apparatus for determining the IC delay quickly by using multiple processors and analyzing multiple pins simultaneously. Also disclosed is the method of ordering the pins to allow the application of the parallel processing technique.

Abstract: The system and method of the present invention enable the effective and efficient determination of the misalignment between openings located in the contact layer and the interconnect layer, respectively. In this way, defective semiconductors produced in semiconductor wafer fabrication can be readily identified and segregated for shipment to customers. A single multifunctional structure formed in the contact layer can be used to determine the alignment accuracy of the contact layer and the interconnect layer by (a) inline visual inspection and (b) determination of the end of line electrical resistance properties of the semiconductor wafer. Hence the use of the multi-functional aspects of this invention eliminates the correlation issues with the structure.

Abstract: The plurality of memory cells of a dynamic random access memory (DRAM) are formed in a well of one majority carrier type, and the well is located in a substrate of the other majority carrier type. The well electrically isolates the memory cells from electrical noise signals created by current in the substrate and charged carriers created by alpha particles. The well is connected at multiple spaced-apart locations to a referencing conductor, to maintain the well at a uniform potential in response to noise. The memory cells are formed in a single well, or groups of the memory cells are each formed in a separate well. A shielding conductor, such as the mesh or an integrally continuous layer of metal which is spaced from the memory cells, overlays a matrix of the memory cells and shields then from the effects of noise.

Abstract: A method for transferring data from a first clock domain to a second clock domain. A first clock signal is generated for the first clock domain from a base clock signal. A second clock signal is generated for the second clock domain from the base clock signal. A phase relationship is detected between the first clock signal and the second clock signal. Data is transferred from the first clock domain to the second clock domain using the phase relationship between the first clock signal and the second clock signal.