Abstract: A method and apparatus for efficiently posting entries to a queue within the data processing system. Entries are posted by first processor with the entries being handled by second processor in the data processing system. The interrupt state associated with the queue is checked by the first processor. If the interrupt state is clear, then the entry is posted to the queue. This interrupt state is cleared only when all entries have been cleared from the queue by the second processor. In this manner, an efficient posting of entries to the queue may be accomplished.

Abstract: An adaptive error detection and correction apparatus for an Asynchronous Transfer Mode (ATM) network device comprises a sensing unit for sensing a congestion condition in the ATM network and a global pacing rate unit for adaptively reducing a maximum allowable transmission ratio of ATM cells containing information to idle ATM cells in response to a sensed congestion condition. A processor stores a number corresponding to a relatively high maximum allowable transmission ratio in the global pacing rate register in the absence of a sensed congestion condition, and stores a number corresponding to a relatively low maximum allowable transmission ratio in the global pacing rate register in response to a sensed congestion condition. A controller adjusts the maximum allowable transmission ratio in accordance with the number stored in the global pacing rate register.

Abstract: A retrograde well in a CMOS device is formed by using a low energy ion implanter. Dopant atoms are implanted into a bare surface of the device's substrate, in a direction that is orthogonal to the surface of the substrate (for a substrate having a <100> orientation). The well implant can be performed at an energy below 220 keV. Chained implants for a punch-through barrier in the retrograde well can be performed after the well implant. When the substrate is annealed, the punch-through barrier is activated at the same time as the retrograde well.

Abstract: The capacity of a cache memory is substantially reduced over that required for a multi-chip distributed shared memory (DSM) implementation to enable the cache memory, a main memory, a processor and requisite logic and control circuitry to fit on a single integrated circuit chip. The increased cache miss rate created by the reduced cache memory capacity is compensated for by the reduced cache miss resolution period resulting from integrating the main memory and processor on the single chip. The reduced cache miss resolution period enables the processor clock rate to be substantially increased, so that a processor having a simple functionality such as a reduced instruction set computer (RISC) processor can be utilized and still provide the required processing speed.

Abstract: Method of cooling electronic systems an semiconductor devices as well as an electronic system and a semiconductor device with heat dissipating elements. The method includes the steps of providing an electronic system or a semiconductor device with a heat sink including at least a first element having a generally flat shape with a shoulder projecting from one generally flat surface, and configured to thermally engage similar elements. In one embodiment, a first and a second heat sink element are provided, with one of the first and second elements having a protrusion and the other of the first and second elements defining a depression configured to receive and retain said protrusion. Alternatively, the first and second elements may be bonded together with a thermally conductive adhesive.

Abstract: An integrated circuit includes a core region and an input-output (I/O) region which has an I/O slot and a voltage supply slot. First and second voltage supply buses and a bias voltage bus extend along the I/O region through the I/O slot and the voltage supply slot. A bias voltage generator is fabricated in the voltage supply slot and is electrically coupled between the first and second voltage supply buses. The bias voltage generator has a bias voltage output which is electrically coupled to the bias voltage bus. A buffer is fabricated in the I/O slot for interfacing with the core region. The buffer includes a bias voltage input which is electrically coupled to the bias voltage bus.

Abstract: A system for optimizing placement of a cell on a surface of a semiconductor chip is disclosed herein. The cells may belong to nets and may belong to neighborhoods. The system initially calculates affinities based on repositioning the cell. The system then combines affinities and repositions cells based on these combined affinities. The system then computes a cost function and repeats the combining, repositioning, and computing functions a predetermined number of times.

Abstract: An application specific integrated circuit having an embedded microprocessor and core including a memory array, self tests at full operational speed utilizing the computational power of the embedded microprocessor for deterministic testing performed by core specific test algorithms implemented in the assembly code of the embedded microprocessor.

Abstract: A method in a semiconductor process for forming a layer of a selected compound on a substrate of a semiconductor device. A layer of titanium is formed on the substrate as a sacrificial layer. The layer of titanium is reduced using a gaseous form of a fluorine containing compound in which the fluorine containing compound includes the selected compound that is to be formed on the substrate of the semiconductor device.

Abstract: A substrate holder assembly for retaining a substrate during chemical mechanical polishing is described. The substrate holder assembly includes: (i) a backing plate including a contact surface adapted for supporting components of the substrate holder assembly and the substrate; (ii) a shim positioned adjacent the contact surface of the backing plate for applying pressure on the substrate during chemical-mechanical polishing; and (iii) a carrier film disposed adjacent the shim such that at least a portion of the carrier film adjacent the shim protrudes outwardly.

Abstract: The invention provides exemplary systems and methods for releasably securing a data storage device within a data storage system. In one exemplary embodiment, the invention comprises a cabinet which defines an enclosure. The data storage device is removably held within the enclosure. A cover is further provided which comprises a pivot end and a latch end. The pivot end is pivotally attached to the data storage device so that pivoting of the cover will release the data storage device at least partially from the enclosure. A cover latch is operably attached to the latch end, with the cover latch engaging the data storage device to prevent pivoting of the cover when the cover is closed.

Abstract: The present invention advantageously provides a method for conditioning a polishing pad used for chemical mechanical polishing of a semiconductor wafer surface. The method involves directing a fluid at a relatively high pressure toward the surface of the pad, thereby roughening the surface of the pad and removing particles embedded in pores of the pad. This process provides for uniform conditioning across the surface of the pad and excludes the use of particles which might become disposed on the pad, unlike some other conventional conditioning methods. The exclusion of abrasive particles prevents scratching of wafers which may subsequently undergo CMP using the polishing pad. The conditioning fluid hereof may, among other things, be a typical CMP slurry or variation thereof, or may be deionized water.

Abstract: Apparatus and method for testing of memory locations containing both test data and test check bits are provided. The apparatus includes a memory controller that communicates with memory devices. In a test mode of operation using a test mode control bit, the memory controller receives test data, together with test check bits that have values corresponding to at least some of the values of the test data. The test data and test check bits are written to desired memory locations of the memory devices. The memory controller is involved in a subsequent read of these same memory locations and receives the test data and test check bits from those previously written memory locations. The memory controller determines whether a correspondence exists between the test check bits that were written and the test check bits that were read. Any lack of correspondence is indicative of one or more memory location faults.

Abstract: An optical system is provided with an adaptable window element at a Fourier plane for spatial filtering. Having a window element made up of individually addressable pixels provides a substantial improvement in the spatial filtering adaptability and precision. When combined with a computer and sensor, the window may become part of a negative feedback loop, thereby providing the optical system with more consistent reproducibility, higher reliability with graceful degradation, and more precise control over final results.

Abstract: A Motion Picture Experts Group (MPEG) multiplexed data bitstream includes encoded video and audio data units, which are prefixed with headers including Presentation Time Stamps (PTS) indicating desired presentation times for the respective data units. The data units are decoded, and presented at a fixed time after decoding, such that the fixed time can be subtracted from the PTS to provide a desired decoding time. The bitstream is parsed, the video and audio headers are stored in video and audio header memories, and the associated video and audio data units are stored in video and audio channel memories respectively. A first interrupt is generated each time a header is stored, and a host microcontroller responds by storing the PTS from the header and the starting address of the corresponding data unit in the channel memory as an entry in a list.

Abstract: A process of making an IC wafer including a surface with improved uniformity, planarity and a reduced likelihood of creating stringers is disclosed.

Abstract: A cell scheduler for a distributed shared memory switch architecture including a controller for scheduling transmissions of cells from output queues of the switch structure pursuant to one of several different scheduling modes. The controller receives a mode selection input, segregates the output queues into groups, assigns priority rankings to the groups, and applies one of scheduling disciplines at each group of output queues as determined by the mode selection input and the priority rankings. The groups of output queues include a group of per-Virtual Channel (VC) queues and at least one group of First In-First Out (FIFO) queues. The scheduling disciplines include a Weighted Fair Queuing (WFQ) scheduling discipline applied by the controller at the group of per-VC queues and a Round Robin (RR) scheduling discipline applied by the controller at the at least one group of FIFO queues. The priority rankings comprising a highest priority ranking which is assigned to the group of per-VC queues.

Abstract: An integrated circuit die includes a plurality of semiconductor cells and first and second power supply conductors. The power supply conductors have different relative polarities and are electrically coupled to the plurality of semiconductor cells. A power supply de-coupling capacitor is formed within the die and is electrically coupled between the first and second power supply conductors.

Abstract: An analogue to digital converter system for digitizing a stream of analogue symbols, the analogue to digital converter system includes an analogue to digital converter for sampling the symbols at predetermined sample timings and a feedback loop for adjusting the sample timings. The feedback loop includes an eye opening detector connected to an output of the analogue to digital converter and responsive to successive digitized symbol samples to determine eye opening signals. The eye opening detector includes a deviation detector for determining a deviation signal representative of a deviation of a digitized symbol sample value with respect to a mean sample value. Preferably, a variance measurement calculator calculates the variance of these deviations. A feedback control is responsive to successive eye opening signals to generate timing control signals for adjusting the sample timings.

Abstract: An A/D converter has an auto-zeroed latching comparator with an input offset voltage. The latching comparator is repetitively switched between an offset adjustment mode and a conversion mode. When the comparator is in the offset adjustment mode, the comparator compares the reference voltage to itself and generates an offset measurement output based on the comparison. A feedback circuit adjusts the input offset voltage based on the offset measurement output. When the comparator is in the conversion mode, the comparator compares the input signal to the reference voltage and generates the digital output signal based on the comparison.