Abstract: A method for maintaining login service parameters includes a step of allocating space for and storing a login service parameter portion of a logged in port. A login service parameter of a logged in port is then compared with stored login service parameter structures. If the login service parameter of the logged in port, except for a login service parameter portion thereof, is identical with one of the stored login service parameters, a step of adding a first pointer to that stored login service parameters structure into the stored login service parameter portion structure is carried out. A new login service parameter portion structure is allocated and the process repeated, thereby creating a linked list of login service parameter portion structures, each login service parameter portion structure pointing to both the stored login service parameter structure and to a next login service parameter portion structure.

Abstract: A semiconductor package having positioned therein a protection layer which protects the integrated circuit chip from electrostatic discharge (ESD) damage. The protection layer is made of a material that has at steady state a high electrical resistance, but when a high ESD potential is applied to it, it becomes highly conductive. A preferred material is SurgX.TM., which is a polymer. The layer is positioned to shunt the potential away from the chip, and can be positioned operatively between a signal lead and a power plane or between different signal leads. That is, the protection layer can be sandwiched between the lead and the conductive member, or the lead can be within the layer. Another preferred construction incorporates the protection material in a tape construction as a thin layer sandwiched between and bonded to a layer of leads and a ground plane.

Abstract: A DBS receiver front end which includes a tuner chip and a demodulator/decoder chip. The tuner chip converts a receive signal to a baseband signal using a tuning frequency signal generated from a tank circuit. The design of a package for the tuner chip maximally spaces the pins associated with high frequency signals by placing them on opposite sides of the chip (in the case of two high frequency signal sources) or (in the case of three high frequency signal sources) in a triangle formation with widely spaced vertices wherein at least two of the pins are adjacent to corners of the package. For two or more high frequency signal sources, a good determination of pin locations can be determined according to the formula P.sub.i =C+i.multidot..left brkt-bot.N/M.right brkt-bot., i=1, . . . , M, where P.sub.i are the pin numbers, N is a total number of pins around the perimeter of the package, M is a total number of the high frequency signal sources, and C is an offset number.

Abstract: A first-in-first-out (FIFO) memory system. The FIFO memory system contains a first fall-through FIFO having an input and an output. A pointer-based FIFO having an input and an output, wherein the input of the pointer-based FIFO is connected to the output of the first fall-through FIFO. The FIFO memory system also includes a second fall-through FIFO having an input and an output, wherein the input of the second fall-through FIFO is connected to the output of the pointer-based FIFO, wherein data placed into the input of the first fall-through FIFO appears at the output of the second fall-through FIFO in a first-in-first-out basis.

Abstract: A wrap back test system and method for providing local fault detection within a section of an integrated I/O interface core device on an integrated circuit is disclosed. The system and method of this invention is suitable for use in any I/O interface having both a transmitter and a receiver section. The wrap back of input test data, prior to reformatting for transmission, to the receiver's data alignment stage permits fault detection within the core of an integrated I/O interface. By illustration, in a serializer/deserializer I/O, the wrap back of alignment pattern encoded parallel data, prior to serialization, to the receiver's data alignment stage permits identifying faults in just this portion of the I/O transceiver. The wrap back test system and method of this invention permits fault isolation of within the boundaries of the I/O core and independent of external logic or testers.

Abstract: In a SCSI controller, unexpected messages are automatically received in response to an attention signal by receiving all of the bytes constituting the message and storing those bytes in an available register file selected from a plurality of register files in the controller. Once the entire message has been received and stored, a determination of an appropriate response is initiated. The register files are also used to hold selection information during a bus-initiated selection, so additional architecture is not required.

Abstract: A method of depositing a low carbon content, high density TiN thin film on a substrate. A substrate is placed within a deposition chamber, and the pressure within the deposition chamber is adjusted to the deposition pressure. A portion of the total thickness desired of the TiN thin film is deposited. The portion of the TiN thin film contains an amount of carbon. Carbon is scavenged from the portion of the TiN thin film deposited by introducing scavenger gases into the deposition chamber. The scavenger gases are chosen so as to be reactive with carbon. The pressure within the deposition chamber is adjusted to the scavenger pressure, and a plasma of the scavenger gases is created within the deposition chamber. The steps from deposition through scavenging are repeated until the desired thickness of TiN is deposited, and the substrate having the desired thickness of TiN deposited thereon is removed from the deposition chamber.

Abstract: A memory device which tests the memory array under typical operating conditions. In one embodiment, the memory device incorporates a heating element to heat the memory array to a predetermined operating temperature, and a BIST (built-in self test) unit to test the memory array at the predetermined operating temperature. This may advantageously provide a method for detecting and repairing faulty memory locations that would not normally test faulty under initial power-up conditions. Broadly speaking, the present invention contemplates a memory device which comprises a memory array and a heating element on a substrate. The memory array is configured to receive a read/write signal on a read/write line, configured to receive an address on an address bus, configured to provide data to a data bus when the read/write signal indicates a read operation, and configured to store data from the data bus when the read/write signal indicates a write operation.

Abstract: A low-gain, low-jitter VCO circuit implemented in CMOS provides center frequency adjustment to overcome process variations. Further, noise immunity is improved by using a separate feedback loop to provide the nominal current biasing for the oscillator chain. This feedback loop coarsely sets the center frequency. The actual control of the oscillation frequency is achieved by a second current source, whose output is added to the nominal bias current to provide a total bias to the oscillator. This second current source "fine tunes" the oscillator frequency responsive to a control signal. Because two separate current sources are used, the circuit can realize a high oscillation frequency with a low VCO gain. Another feature provides for adjusting the center frequency in response to a digital input word provided via external pins, or from internal logic or memory. The center frequency thus can be calibrated by measurement at the time of manufacture, or changes later by the end user or by other circuitry.

Abstract: The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.

Abstract: A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.

Abstract: An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special "checkerboard" arrangement also provided. Connections between the bumps and the edge of the die surface are shown.

Abstract: A method is presented for depositing a low stress, highly conformal metal thin film, such as tungsten, on a substrate. A substrate is provided, and is heated to a first temperature. A first portion of the metal thin film is deposited on the substrate by reacting a first set of process gases. The deposition of the first portion of the metal thin film is stopped after a first length of time, and the substrate is heated to a second temperature, which is greater than the first temperature. A second portion of the metal thin film is deposited on the substrate by reacting a second set of process gases. The second portion of the metal thin film comprises the same metal as the first portion of the metal thin film. The deposition of the second portion of the metal thin film is stopped after a second length of time. Semiconductor devices having a low stress, highly conformal thin film are also described.

Abstract: A process for optimizing the layout of an integrated circuit (IC) design is described. The optimization process includes selecting a segment of a conductive line to be modified. The segment is selected based upon its location between a first line and a second line and is separated from these lines by unequal distances, such that the segment is close enough to the first line such that a sensitive area that is susceptible to damage from particle contamination exists. The process also includes repositioning the selected segment such that the distance between the segment and the first line is increased and the distance between the segment and the second line is decreased.

Abstract: A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.

Abstract: A method for dynamic reconfiguration of a message-passing interface from a Push model to a Pull model is disclosed. In the Push model, a host computer device moves data stored in a host local memory to an I/O peripheral shared memory, whereas in the Pull model, the I/O peripheral moves data from the host's shared memory to a local memory of the I/O peripheral. To dynamically reconfigure the message passing interface from the Push to the Pull model, the hosts waits for the I/O peripheral to cycle through power-on/reset, locates the I/O peripheral's inbound and outbound queues in memory, directs the I/O peripheral to clear its outbound queue of messages from previous inbound messages and initializes the allocated message frames as free messages. The host then posts a message to the I/O peripheral inbound queue instructing the I/O peripheral to initialize in the Pull model. The I/O peripheral then posts any messages currently being processed to the I/O peripheral outbound queue.

Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.

Abstract: A stiffener device for use with a flip chip packaging assembly including a generally rectangular, plate-like member having a substantially uniform thickness. At each of the rectangular plate-like member is a curved chamfer portion extending from an upper surface to a lower surface thereof, and defined by a chamfer edge commencing at one side edge forming the respective corner and terminating at an opposite side edge of the respective corner. Each curved chamfer portion is adapted to receptively accommodate a respective mounting bolt therethrough. The fabrication of the stiffener device is formed from a single stamping or punching operation in a manner maintaining a substantially planar upper surface and lower surface.

Abstract: The present invention presents a mobile station of a wireless communications system such that when the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and thus all high-frequency clocks derived from it are turned off. Only a low-frequency clock remains operating at all times to clock the sleep logic.

Abstract: An object-oriented, multi-media architecture provides for real-time processing of an incoming stream of pseudo-language byte codes compiled from an object-oriented source program. The architecture includes a plurality of processors arranged for parallel processing. At least some of the processors are especially adapted or optimized for execution of multi-media methods such as video decompression, inverse discrete cosine transformation, motion estimation and the like. The architecture further includes a virtual machine computer program that reconstructs objects and threads from the byte code stream, and routes each of them to the appropriate hardware resource for parallel processing. This architecture extends the object-oriented paradigm through the operating system and execution hardware of a client machine to provide the advantages of dedicated/parallel processors while preserving portability of the pseudo-language environment.