Abstract: The present invention relates to an apparatus for generating a low pressure plasma circulating in a planar direction within a process enclosure. The invention generates plasma having substantially uniform density characteristics across a planar axis. The invention achieves improved uniformity of the plasma density by delivering more radio frequency power toward the periphery of the circulating plasma than toward the center of the plasma. Increasing the periphery power to the circulating plasma compensates for increased plasma losses due to interaction with the side walls of the process containment enclosure.

Abstract: A substrate includes a non-conductive support layer and a plurality "n" of conductive leads disposed on the support layer. The leads are arranged in a generally radial pattern about a central point on the support layer, each of the leads having a width "w" and spaced a distance "d" from one another at their innermost ends, thereby forming a generally square opening of side dimension "s". The substrate accommodates semiconductor dies ranging in size from smaller than the opening, to approximately equal to that of the opening, to substantially larger than the opening, such as four times the size (linear dimension) of the opening. The die is bonded to the substrate. Other elements of a semiconductor device assembly are added to the resulting structure. Method and apparatus are disclosed.

Abstract: Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between contacts on opposite sides of the die, and jumpered connections between contacts on the same side of the die. Various multi-chip configurations are described. Certain of these flip-chip configuration dramatically increase the ratio of I/O area (periphery) to footprint area, permitting larger numbers of I/O points within a given assembly footprint than would otherwise be possible in a single die configuration.

Abstract: A novel channel buffer management scheme for a video decoder minimizes the amount of memory allocated to buffer a video bitstream received from a transmission channel. A channel buffer accumulates picture data encoded in a video bitstream received from a fixed rate channel. Picture data is read out of the channel buffer by a video decoder immediately after a predetermined or expected amount of bitstream data is received by the channel buffer. Picture decoding, reconstructing, and displaying operations are synchronized to permit the transfer of picture data from the channel buffer to the decoder whenever all of the data bits comprising a picture are received in the channel buffer. A microcontroller monitors and regulates the operation of the novel channel buffer management scheme to avoid overflow or underflow of bitstream data in the channel buffer.

Abstract: A process is described for forming a low dielectric constant insulation layer on an integrated circuit structure on a semiconductor wafer by first forming a composite layer, comprising one or more extractable materials and one or more matrix-forming insulation materials, over an integrated circuit structure on a semiconductor wafer, and then selectively removing the extractable material from the matrix-forming material without damaging the remaining matrix material, thereby leaving behind a porous matrix of the insulation material. In one embodiment, the composite layer is formed from a gel. The extractable material is removed by first dissolving it in a first liquid which is not a solvent for the matrix-forming material to form a solution. This solution is then removed from the matrix-forming material by rinsing the matrix in a second liquid miscible with the first solvent and which also is not a solvent from the matrix-forming material.

Abstract: A boat transport is fabricated to receive either pins-down or pins-up type semiconductor device assemblies, without damaging the pins, and to position the body of the semiconductor device assembly for subsequent packaging processes. The boat transport includes a planar platform for supporting a peripheral portion of the package body. A single large cutout through the platform receives all of the pins of the semiconductor device assembly. Guides which extend downward from the platform along each side (edge) of the cutout prevent lateral and rotational movement of a pins-down package. Other guides, which ascend upward from the platform along each side (edge) of the cut out, prevent pins-up packages from lateral and rotational movement. Additional cutouts through the platform accommodate chip capacitors.

Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.

Abstract: A compact MOS type active device is constructed at least partially in an opening in an insulation layer, such as an oxide layer, above a portion of a semiconductor substrate forming a first source/drain region of the MOS type active device. A semiconductor material, on the sidewall of the opening, and in electrical communication with the portion of the substrate forming the first source/drain region of the device, comprises the channel portion of the MOS device. A second source/drain region, in communication with an opposite end of the channel, is formed on the insulation layer adjacent the opening and in electrical communication with the channel material in the opening. A gate oxide layer is formed over the channel portion and at least partially in the opening, and a conductive gate electrode is then formed above the gate oxide.

Abstract: A high performance graphics applications controller having a core processor and a coprocessor to independently perform desired graphics functions is provided. The core processor and the coprocessor divides processing tasks to speed execution and to reduce the burden on the host CPU. A direct memory access (DMA) controller cooperates with the coprocessor to generate source and destination addresses and employs a unique set of commands to speed operation. The core processor employs a local CPU and data and address catches to locally perform desired graphics operations independently but in conjunction with the coprocessor. The present invention has particular application with smart terminals and wherever pixel oriented data is required.

Abstract: A plurality of unsingulated dies on a wafer may be individually powered up using various "electronic mechanisms" on the wafer, and connecting the electronic mechanisms to the individual dies by conductive lines on the wafer. The electronic mechanisms are capable of powering-up a single die or groups of the dies, and electronically "walking through" the entire plurality of unsingulated dies. Redundant conductive lines may be provided. Diodes and/or fuses may be provided in conjunction with the conductive lines, to protect against various faults which may occur in the conductive lines. Redundant electronic selection mechanisms may also be provided to ensure the ability to selectively power up the dies.

Abstract: A technique for simultaneously forming large numbers of solder ball (or bump) contacts on a surface of a substrate is described. A dissolvable film carrier is provided with holes arranged in a shape to correspond to an array of contact pads on a substrate. The holes are filled with solder. The film carrier retains the solder. The carrier is placed over the surface of the substrate and is heated, causing the solder to re-flow and to wet and to adhere to the contact pads. The carrier, which resists the re-flow temperature, maintains the shape of the solder contacts while cooling. After cooling, the film carrier can be removed from around the solder contacts with a suitable solvent.

Abstract: A method of cleaning semiconductor substrates after polishing, particularly chem-mech polishing a semiconductor substrate to planarize a layer, to remove excess material from atop a layer, and to strip back a defective layer is disclosed. Aluminum oxide particles having a small, well controlled size, and substantially in the alpha phase provide beneficial results when polishing. A phosphoric acid cleaning solution is used. The aluminum oxide particles are soluble in the phosphoric acid solution, which does not significantly attack silicon dioxide. The phosphoric acid solution can include a small concentration of hydrofluoric acid to aid in removing silicon dioxide detritus from the surface of the wafer.

Abstract: An integrated circuit device package of this invention includes a flexible substrate having an upper patterned insulative layer, and a lower patterned conductive layer including a plurality of package leads. An integrated circuit die is fixed within a void of the upper surface of the flexible substrate, and is provided with electrical connections to the package leads. A rigid upper protective layer is provided to substantially enclose the integrated circuit die, and at least partially cover the top surface of the upper insulative layer. The integrated circuit device package further comprises a rigid or semi-rigid lower protective layer opposite the upper protective layer. The rigid lower protective layer is prefomed, and preferably is made from a material selected from the group consisting of rigid ceramic, glass, plastic, and combinations thereof.

Abstract: A heat sink (44-48) is detachably mechanically connected to an electronic component package (10) by means of a pair of mutually spaced and parallel spring rods (16, 18) that are fixed to the electronic component package and span a recess (14) formed in a surface of the package. The heat sink is formed with a projecting latching member (50) having a short shank (52) on the end of which is formed a laterally outwardly extending flange (60). The flange has shoulders (62) that slope outwardly and away from the heat sink body and distal ends on which are formed cam surfaces (66) that slope inwardly away from the heat sink body. The latching member (50) of the heat sink is pressed into the electronic component package recess between the resilient rods (16, 18) to force the rods apart and to pass the outer most ends (64) of the flange this causes the rods to contact the flange shoulders (62) in a slightly outwardly bowed position of the rods.

Abstract: A technique for improving power distribution to an semiconductor die while simultaneously reducing thermally-induced mechanical stresses on bond pads in semiconductor device assemblies is accomplished by providing the signal-carrying bond pads in a collinear arrangement along an axis of the die, and providing power-carrying bond pads in an off-axis location. The on-axis configuration of signal-carrying bond pads minimizes lateral thermal displacements of the bond pads relative to the axis, which minimizes any longitudinal, compressive end displacements of leadframe fingers or bond wires, thereby minimizing thermally induced mechanical stresses of the bond pad interfaces to the die. The positioning of the power-carrying bond pads off-axis reduces the length of internal (to the die) wiring required to connect circuitry on the die to the power-carrying bond pads.

Abstract: A technique for simultaneously forming large numbers of solder ball (or bump) contacts on a surface of a substrate is described. A mold is provided for receiving a substrate. Recesses in the mold are shaped to form contacts of a desired size, and are arranged to align with contact pads on the surface of the substrate. When the substrate is inserted into the mold and the mold is closed, the contact pads align with the recesses. Molten solder is introduced into the recesses and, upon cooling, forms conductive raised bump contacts on the contact pads. The substrate is then removed from the mold. Various features of the invention are directed to forming "tall" contacts with an aspect ratio (height to width ratio) of greater than 1:1, processing more than one substrate at a time, processing substrates of different sizes, and processing substrates with different contact patterns.

Abstract: A method of interactive feedback in semiconductor processing is provided which compensates for lithographic proximity effects, reactive ion etch loading effects, electromigration and stress due to layering.

Abstract: A logic compiler wherein verification of a generated circuit model is performed automatically by comparing the operation of the circuit model with that of a corresponding mathematical behavior model. A novel user interface and circuit model generation means enables the user to obtain, in real time, performance specifications on the circuit selected by the user as well as incurring other benefits.

Abstract: Fine, sub-micron line features and patterns are created in a sensitized layer on a semiconductor wafer by a beam of low wavelength radiation, such as X-rays or Gamma-rays. A continuous stream of such radiation is gated on and off by a shutter mechanism comprising a distortable-surface device and a beam-blocking device. The distortable-surface device is a surface acoustic wave device, a magnetostrictive device, or the like. The beam-blocking device is a beam stop, such as a knife edge, an aperture, or the like. The distortable-surface device can be selectively caused to reflect an incident beam of radiation past or into the beam-blocking device. In this manner, a continuous stream of radiation, such as from a pellet of Cobalt-60, can be quickly and precisely gated on and off to impact and to not-impact the semiconductor wafer, respectively. By moving either of the reflected beam or the semiconductor wafer, line features can be created in the sensitized layer on the semiconductor wafer.

Abstract: An improved Faraday Cage is provided for use in reducing ion damage to semiconductor wafers during plasma etching. The improved Faraday Cage consists of a cylindrical metallic chamber having a cap at one or more ends. Semiconductor wafers are placed within the Cage and the Cage is suitably disposed within a plasma etcher. The caps substantially reduce the amount of harmful radiation which can enter the Cage and thereby ion damage to the wafers contained therein. The improved Faraday Cage can be conveniently integrated with a barrel-style plasma etcher by securing one of the Cage caps to the door of the plasma etcher such that opening and closing the door serves to disengage and engage one of the caps from the Cage.