Abstract: A configuration including a grounding mechanism protects a semiconductor device from electrical overstress damage during processes, such as an RIE process, where an electrical charge can build up on the semiconductor device. According to an exemplary embodiment, the configuration secures a semiconductor device such that a die of the device is exposed to an electrically charged environment and electrically conductive terminals of the device are isolated from the electrically charged environment. The grounding mechanism electrically connects each of the electrically conductive terminals to a ground potential while the die is exposed to the electrically charged environment.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A routing multiplexer system provide p outputs based on a selected permutation of p inputs. Each of a plurality of modules has two inputs, two outputs and a control input and is arranged to supply signals at the two inputs to the two outputs in a direct or transposed order based on a value of a bit at the control input. A first p/2 group of the modules are coupled to the n inputs and a second p/2 group of the modules provide the n outputs. A plurality of control bit tables each contains a plurality of bits in an arrangement based on a respective permutation. The memory is responsive to a selected permutation to supply bits to the respective modules based on respective bit values of a respective control bit table, thereby establishing a selected and programmable permutation of the inputs to the outputs.

Abstract: The present invention is directed to a system and method for optimizing establishment of mirrored data. In an aspect of the present invention, a method of tracking changes to mirrored storage system including a first storage device and a second storage device may include creating a map including at least one map entry having an identifier suitable for describing a range of addressable data blocks. The range of addressable data blocks includes at least one data block modified after operation of the first storage device is suspended. At least one of a range of addressable data blocks described by at least one map entry of the map and a number of map elements copied per establish command is specified. The map including the at least one map entry on the second storage device is stored. The map is suitable for being utilized to restore data stored on the second storage device to at least one of the first storage device and a third storage device.

Abstract: A receive deserializer circuit which frames parallel data utilizes a skip-bit technique for aligning a predefined data reference pattern with a word clock. The receive deserializer circuit includes a sampling flip flop which receives serial data including a data reference pattern. The sampling flip flop samples and retimes the serial data to a recovered clock. A demultiplexer then deserializes the retimed serial data into a parallel data word which is timed to a word clock from a clock generator. A comparator makes comparisons of the parallel data word with a preset data reference pattern until a match results. A logic controller interprets whether the output of the comparator is a match and generates a shift pulse following each comparison which does not result in a match. The clock generator divides the recovered clock into eight phase clocks. One of the phase clocks is a word clock.

Abstract: A test vehicle a system and method for evaluating an interconnect module manufacturing process while dynamically testing performance with high-speed operational frequencies is disclosed. An interconnect module designed at many of the manufacturing process limits offers complete and fast failure analysis so that manufacturing defects can be quickly located and the process improved. Failure analysis, particularly on 90 nm technologies and beyond is becoming extremely difficult. At-speed testing is also becoming very important to the yield and reliability of products. This invention incorporates a self-timed speed circuit that can detect subtle resistive faults and also show the exact location in the array where the speed fault occurred based on test program datalogs from scan flip flops.

Abstract: A test structure for an integrated circuit having a first underlying conductive layer. A first nonconductive layer is disposed over the first underlying conductive layer, and a first overlying conductive layer is disposed over the first nonconductive layer. First conductive vias form electrical connections between the first underlying conductive layer and the first overlying conductive layer. A second overlying conductive layer is disposed over the first nonconductive layer, but the second overlying conductive layer does not make electrical connections to the first underlying conductive layer. The test structure also has a second underlying conductive layer. A second nonconductive layer is disposed over the second underlying conductive layer, with a third overlying conductive layer disposed over the second nonconductive layer. The third overlying conductive layer does not make electrical connections to the second underlying conductive layer.

Abstract: A method for minimum metal consumption power distribution includes the steps of forming a circuit having a plurality of circuit components on an electrically insulated substrate and forming a plurality of supply voltage regulators on the electrically insulating substrate wherein each of the plurality of supply voltage regulators is located adjacent to each of the plurality of circuit components respectively, and each of the plurality of supply voltage regulators is connected to each of the plurality of circuit components respectively for generating a regulated voltage rail output to each of the plurality of circuit components respectively.

Abstract: A capacitor has a titanium nitride layer deposited on a silicon substrate for stress reduction and adherence promotion, and a layer of tantalum is deposited thereon. The tantalum layer is oxidized to produce a tantalum pentoxide layer. A top electrode of metal or polysilicon is then deposited on the tantalum pentoxide layer. The top electrode may be made from polysilicon or a similar semiconducting material so that a space charge layer will form in the electrode which will change the rate at which the capacitor charges and discharges. Alternatively, the top electrode may be made from metal to provide an optimal linear response for use in analog applications. Further, an undoped polysilicon layer may be provided above the tantalum pentoxide layer to store charge for non-volatile memory applications. For this purpose, polysilicon can be used to form the top electrode; alternatively, materials such as silicon nitride may be used.

Abstract: A mask used for imaging nearly dense features in a substrate. Scatter dots are disposed on the mask in proximity to the nearly dense features, where the scatter dots adjust photon levels of the nearly dense features to a desired level. The adjustment is controlled by selective adjustment of a duty cycle and degree of stagger of the scatter dots. In this manner, the scatter dots adjust the optical properties of the nearly dense features to be very similar to the optical properties of dense features, which enables more accurate imaging of the nearly dense features on the substrate. However, because the scatter dots are discontinuous, they do not overcorrect in the same manner that a scatter bar formed at a minimum resolution might overcorrect. Further, there is a reduced likelihood that the scatter dots would actually print on the substrate.

Abstract: Embodiments of the invention include a method for electro chemical mechanical polishing of a substrate. The process includes flowing an electro chemical mechanical polishing (ECMP) slurry having a high viscosity with a polishing agent over a portion of the substrate. Electrical current is passed through the slurry and substrate. The electrical current, in conjunction with the abrading action of the slurry as it flows over the surface of the substrate, serves to remove at least a portion of the metal layer from the substrate. The invention also includes various slurry embodiments.

Abstract: A method for reducing data/parity inconsistencies due to a storage controller failure in computer storage systems with dual, independent storage controllers and a number of logical volumes comprising one or more physical disk drive devices includes recognizing a failure of the storage controller; assuming access control of the volume; and thereafter, performing at least one write to the volume, wherein, for a predetermined number of writes (N) to the volume after failure of the storage controller, new parity is calculated for the write using new data and other data (Method 2). The predetermined number of writes (N) is at least equal to or greater than the queue depth of the failed storage controller (i.e., the number of I/O operations that the failed storage controller may service at a given time. The method may be implemented by each storage controller of the computer storage system.

Abstract: An input/output controller that allows independent and configurable reduction of clock speeds to its embedded processors when they are not in use to save average power consumption. The processor clock speeds are restored when new input/output requests are received.

Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.

Abstract: A method and apparatus for recording digital video and/or audio signals include input audio and video interfaces, a memory, a video frame selector, and output audio and video interfaces. In an alternate embodiment, the method and apparatus include input audio and video interfaces, a first memory, a second memory for playback, and output audio and video interfaces. Another embodiment further includes a memory optimizer for maximizing a chosen criterion such as audio duration, image capture frequency or pixel resolution.

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes selected from: (a) an organofluoro silane containing two silicon atoms linked by one oxygen atom; (b) an organofluoro silane containing two silicon atoms linked by one or more carbon atoms, where the one or more carbon atoms each are bonded to one or more fluorine atoms, or to one or more organofluoro moieties, or to a combination thereof; and (c) an organofluoro silane containing a silicon atom bonded to an oxygen atom. The invention also provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes that include one or more organofluoro silanes characterized by the presence of Si—O bonds.

Abstract: A transmission line for an integrated circuit (IC) is composed of an assemblage of connected, individual transmission line portions. According to one embodiment, the transmission line assemblage includes two or more (i.e. a plurality of) vertically disposed, electrically connected, individual transmission line portions. Each transmission line portion is electrically connected to a vertically adjacent transmission line portion. Preferably, each transmission line portion is formed in a separate layer of the IC with connections between the transmission line portions formed by vias. As such, the subject transmission tine exhibits a low capacitance and a characteristic impedance that is easily driven. In another form, the subject invention is a system, process and/or apparatus for forming a transmission line on an integrated circuit (i.e. an on-chip transmission line). The transmission line is formed of an assemblage of connected, individual transmission lines such as those described above.

Abstract: Multiple processors of a multiprocessor system are placed into a debug mode of operation approximately simultaneously when one processor initially enters the debug mode as a result of incurring a debug event. The other processors enter the debug mode as a result of the one processor asserting a debug event signal upon initially entering the debug mode. A logic circuit associated with each processor responds to any debug event signal asserted by another processor and the failure of its associated processor to assert a debug event signal, to assert an external debug break signal to the associated processor and place the associated processor into the debug mode.

Abstract: The present invention is directed to an interactive representation of structural dependencies in semiconductor design flows. In an aspect of the present invention, a method for providing interactive representation of structural dependencies in a semiconductor design flow as implemented by an information handling system may include detecting a modified value of a parameter of the semiconductor design flow. At least one parameter dependent on the changed parameter is identified, the dependent parameter previously entered by a user.

Abstract: As technology in the semiconductor industry advances, semiconductor devices decrease in size to become faster and less expensive per function. Smaller semiconductor devices, particularly MOSFETs, are increasingly sensitive to Electrostatic Discharge (ESD). ESD can either destroy or permanently damage a semiconductor device. Embodiments of the present invention assist in preventing ESD damage to semiconductor devices. An embodiment of the present invention utilizes a diode connected to the substrate terminal of a MOSFET. Under normal operation up to the maximum operating voltage, the diode and MOS devices are open and do not conduct. The diode triggers when an ESD pulse causes the reverse breakdown voltage of the diode to be exceeded. The resultant current switches a connected MOS device, operating in bipolar mode, to dissipate the damaging ESD pulse. The ESD pulse is shunted to ground, thereby avoiding damage to the rest of the device.