Abstract: The present invention is directed to a system and method for providing multidirectional routing. The present invention may provide an arbitrary number of routing layers and an arbitrary direction on each of those layers to provide a smaller die size and to reduce power consumption by providing more flexibility for net routing directions.

Abstract: A system and method are presented for an external host processor to distribute data to memory devices associated with multiple digital signal processors (DSPs) within an integrated circuit “system on a chip.” A host processor interface in the multi-processor integrated circuit responds to commands from the host processor and provides access to the memory devices. A control register in the interface is directly accessible by the host processor, and is used to generate various control signals in response to host processor commands. A data control register in the interface has a field of write enable bits that directly control write accessibility of the memory devices—if a designated write-enable bit within the data control register is set, the corresponding memory devices are write enabled. An extended address bit in the control register is used to select either instruction or data memory for write access.

Abstract: Clock uncertainty between a receiving cell and a launching cell of a net is estimated by back-tracing a first path from the receiving cell toward the clock source and marking each cell having a predetermined character along the first path. A second path from the launching cell toward the clock source is back-traced to a predetermined marked cell. Clock uncertainty is calculated based on the portion of the first path from the predetermined marked cell to the receiving cell. Clock uncertainty is calculated if a slack does not exceed a margin value. In one embodiment, a clock net in the form of a tree is optimized by forcing a first buffer to the center of gravity of a plurality of buffers having nets without timing violations to maximize a common path from the root to the forced buffer and minimize the non-common paths from the forced buffer to the leaves, thereby minimizing clock uncertainty.

Abstract: The present invention is directed to a simplification method for an arbitrary library. In aspects of the present invention, the method does not rely on specific properties of the library elements and has linear complexity. The present invention may be implemented based on a symbolic simulation in an alphabet which contains 0, 1, symbols of variables, and negations of the variables' symbols. In an aspect of the present invention, a method for reducing redundancy in a simulation through use of a symbolic simulation utilizing an arbitrary library includes receiving a set A of values, the set A including input variables which are elements of the set A. Symbols of the input variables are constructed in which like and similar variables share a like symbol and a similar symbol respectively. A table of output values computed from a table of a Boolean operator employing the constructed symbols of the input variable is formed, the constructed symbols formed to reduce redundancy.

Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Abstract: An IC design is tested on a workstation through a hardware simulator. The workstation includes a co-verification software tool that executes IC firmware to operate the IC design and test the IC design and IC firmware. The co-verification software tool further operates to supply test stimuli to the IC design and to receive responses for analysis. The test stimuli are written in a programming language, which permits ease of testing and analysis of the IC design.

Abstract: A global interconnect distribution system is disclosed. The global interconnect distribution system includes a global interconnect cell capable of producing at least two substantially identical output signals, and a global interconnect coupled to the cell for carrying one of the output signals. At least one wire is also coupled to the cell that is routed adjacent to the global interconnect for carrying the other output signal to provide active shielding for the global interconnect, thereby increasing signal integrity and signal transmission of the global interconnect.

Abstract: A system and method are disclosed for providing a gain control signal for a multilevel read signal. In one embodiment, maximum automatic gain control marks are periodically inserted amongst a series of data fields. The automatic gain control marks include a series of high level marks such that the maximum signal detected in the interior portion of each maximum automatic gain control mark is not reduced by intersymbol interference. Minimum automatic gain control marks are also periodically inserted amongst a series of data fields. The automatic gain control marks include a series of high level marks such that the maximum signal detected in the interior portion of each minimum automatic gain control mark is not reduced by intersymbol interference. In another embodiment, multilevel signals are encoded to facilitate automatic gain control. The effect of a plurality of candidate merge symbols on the residual running total power associated with a current data block is determined.

Abstract: A phase shift mask having transmission properties that are dependent at least in part on an intensity of an incident light beam. The phase shift mask has a mask substrate that is substantially transparent to the incident light beam. A first phase shift layer is disposed on the mask substrate. The first phase shift layer has a refractive index that is nonlinear with the intensity of the incident light beam. The refractive index of the first phase shift layer changes with the intensity of the incident light beam on the phase shift mask. By using a first phase shift layer on the phase shift mask that has a refractive index that is non linear with the intensity of the incident light beam, properties of a light beam transmitted through the first phase shift layer, such as interference patterns in the transmitted light beam, can be adjusted by adjusting the intensity of the incident light beam.

Abstract: A method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.

Abstract: A computer program product, apparatus, and method for correcting errors introduced into a set of data bits during transmission of the set of data bits over a channel includes determining a confidence measure for each data bit based only on the values of one or more of the data bits, each confidence measure representing the probability that the value of the corresponding data bit is correct; and changing the value of a given data bit when the confidence measure for the given data bit indicates that the value of the given data bit is not correct, thereby producing a corrected data bit.

Abstract: A controller for a double data rate synchronous dynamic random access memory (SDRAM) includes an address storage block comprising an address storage register for each of a plurality of priority levels for receiving a memory address of a request from an incoming command queue for each of a plurality of priority levels and a priority logic block coupled to the address storage block wherein the priority logic block comprises a first priority register for storing a register number field for each of the plurality of priority levels, a second priority register for storing a request valid field for each of the plurality of priority levels, and a third priority register for storing a state machine address field for each of the plurality of priority levels.

Abstract: Systems and methods for enhancing slew control of output signals. An output driver receives an input signal and controllably increases the gain of that signal to provide a high quality output signal for use by an electronic device coupled thereto. The output driver includes an operational amplifier that maintains stability of the output signal through a feedback of the output signal. A control circuit supplies a signal to the output driver such that the driver to improve the shape of the output signal as the input signal is applied. After the operational amplifier regains control, the control circuit disengages. One embodiment of the present invention may be particularly useful as a USB output driver.

Abstract: A switched architecture is provided to allow controllers to manage physically independent memory systems as a single, large memory system. The switched architecture includes a path between switches of controllers for inter-controller access to memory systems and input/output interfaces in a redundant controller environment. Controller memory systems are physically independent of each other; however, they are logically managed as a single, large memory pool. Cache coherency is concurrently maintained by both controllers through a shared locking mechanism. Volume Logical Block Address extents or individual cache blocks can be locked for either shared or exclusive access by either controller. There is no strict ownership model to determine data access. Access is managed by the controller in the pair that receives the access request.

Abstract: Logic circuits for logical operations, based on a function fN=x1 OR (x2 AND (x3 OR (x4 AND . . . xN . . . ))) or f?N=x1 AND (x2 OR (x3 AND (x4 OR . . . xN . . . ))), are designed by defining a top portion of the logic circuit based on a pre-selected pattern of 2-input $ and @ gates. The top portion has N inputs and approximately N/3 outputs. A smaller logic circuit is defined having approximately N/3 inputs coupled to the outputs of the top portion. In one embodiment, the circuit is designed for a circuit having N? inputs, where N? is 3n or 2*3n, and the N?-N most significant inputs are set to fixed values. The extra gates are removed resulting in a minimum depth circuit. In another embodiment, the depth is further reduced in some cases by designing a circuit for N-1 inputs and transforming the circuit to an N-input circuit. The $ and @ gates are converted to AND and/or OR gates, depending on the function.

Abstract: A single-chip synchronous optical network (SONET) physical layer device includes first, second and third interface ports. An asynchronous transfer mode (ATM) interface circuit is coupled to the first interface port. A point-to-point protocol (PPP) processing circuit is coupled to the second interface port and the ATM interface circuit. A SONET framer circuit is coupled between the ATM interface circuit and the third interface port and between the PPP processing circuit and the third interface port. The device is programmable to allow multiple standard and non-standard data transmission modes, including transmitting ATM cells in SONET payloads, PPP frames in ATM cells in SONET payloads, PPP frames from a UTOPIA interface in SONET payloads and PPP frames directly in SONET payloads.

Abstract: A plasma edge cleaning apparatus is configured to remove film deposits from a wafer edge. A gas distribution manifold is annular shaped and positioned to provide plasma process gases near the edge of the wafer. A top insulator and a wafer support each include a magnetic coil to generate a magnetic field for shielding the selected portions of a wafer from the generated plasma. The top insulator is positioned above the wafer during edge processing so as to form a small gap between the top insulator and the wafer to prevent plasma from etching active die areas of the wafer.

Abstract: A process for forming copper metal interconnects and copper-filled vias in a dielectric layer on an integrated circuit structure wherein the impurity level of the copper-filled metal lines and copper-filled vias is lowered, resulting in an increase in the average grain size of the copper, a reduction of the resistivity, and more homogeneous distribution of the stresses related to the formation of the copper metal lines and copper-filled vias throughout the deposited copper. The process comprises: depositing a partial layer of copper metal in trenches and via openings previously formed in one or more dielectric layers, then annealing the deposited copper layer at an elevated temperature for a predetermined period of time; and then repeating both the deposit step and the step of annealing the deposited layer of copper one or more additional times until the desired final thickness is reached.

Abstract: A method for decoding an input bitstream is disclosed. The method generally includes the steps of (A) generating an intermediate bitstream having an intermediate encoded format by converting the input bitstream having an input encoded format and an input order, (B) storing the intermediate bitstream in the input order and (C) generating an output signal having an output order by decoding the intermediate bitstream.

Abstract: A method for generating a plurality of timing constraints for a circuit design is disclosed. The method generally includes the steps of (A) identifying a plurality of clock signals by analyzing the circuit design, (B) determining a plurality of relationships among the clock signals and (C) generating the timing constraints for the circuit design in response to the clock signals and the relationships.