Abstract: An apparatus comprising one or more enclosures and a controller. The one or more enclosures may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to one or more drives. An advantageous aspect of the present invention is the ability to support general enclosure wiring when associating data with physical devices, such as associating SES data with physical devices on a fiber channel loop with soft addresses.

Abstract: A substrate that includes a non-electrically conductive core having a first side and an opposing second side. A first electrically conductive layer is disposed on the first side of the core, and a second electrically conductive layer is disposed on the second side of the core. Electrically conductive core vias extend from the first side of the core to the second side of the core. The core vias are disposed in an array. An electrically conductive contact is formed on an upper build-up layer on the first side of the core, and overlies the array of core vias. A first electrically conductive via electrically connects the contact to an intervening build-up layer disposed between the upper build-up layer and the first electrically conductive layer. The first via overlies the core via array. A second electrically conductive via electrically connects the intervening build-up layer and the first electrically conductive layer, where the second electrically conductive via is not disposed over the core via array.

Abstract: A method of forming a metal interconnect in an integrated circuit. A copper layer is formed over dielectric structures on the integrated circuit, where the dielectric structures have an upper level. The copper layer is planarized to be no higher than the upper level of the dielectric structures, without reducing the upper level of the dielectric structures. An electrically conductive capping layer is formed over all of the copper layer, without the capping layer forming over any of the dielectric structures.

Abstract: An apparatus comprising an output circuit, a first processing circuit and a second processing circuit. The output circuit may be configured to generate an output data stream in response to (i) a first intermediate signal, (ii) a second intermediate signal, and (iii) a third intermediate signal. The first processing circuit may be configured to generate the first intermediate signal in response to (i) a processed video signal and (ii) a prediction flag. The second processing circuit may be configured to generate (i) the processed video signal, (ii) the second intermediate signal and (iii) the third intermediate signal in response to an input video signal.

Abstract: A method for generating a compressed representation of a simulated waveform is disclosed. The method may have the steps of: (a) processing circuit model information, (b) identifying a segment of stable repetition; and (c) generating the compressed representation. Step (a) may generate waveform information representing a simulated waveform occurring in the circuit model. Step (b) may identify the segment in the waveform information. In step (c), the compressed waveform information may define the segment by (i) cycle information representing the waveform cycle and (ii) repetition information representing the stable repetitions of the waveform cycle to form the segment.

Abstract: The mask includes a substrate formed of a material having a first index of refraction and a first level of transmittance to a wavelength of light with which the phase shift mask is designed for use. Second portions of the substrate are impregnated with a dopant species, leaving first portions of the substrate unaffected by the dopant species. The second portions of the substrate have a second index of refraction and a second level of transmittance to the wavelength of light. The first index of refraction is not equal to the second index of refraction. The second portions of the substrate shift a phase of the light relative to the first portions of the substrate and thereby increase an effective imaging resolution of the phase shift mask. In this manner, instead of using an etch process or a deposition process to form phase shifting regions of the mask, a doping processing is used instead. Most preferably, an ion implantation process is used.

Abstract: An apparatus comprising an input circuit, a content analyzer, a storage circuit and an output circuit. The input circuit may be configured to generate a first intermediate signal from a plurality of input video signals. The content analyzer circuit may be configured to present one or more flags in response to the intermediate signal. The storage circuit may be configured to (i) store and organize the first intermediate signal into a plurality of sequences each related to one of the input video signals and (ii) generate a second intermediate signal from the sequences. The output circuit may be configured to generate an output video signal in response to the second intermediate signal. The output circuit may be configured to embed tracking information into the output video signal in response to the one or more flags.

Abstract: An apparatus comprising a set-top box and a conversion circuit. The set-top box may be configured to generate output signals in response to a first encoded data signal. The conversion circuit may be configured to present the first encoded data signal in response to a second encoded data signal received from an external source. The first encoded data signal comprises a legacy signal and the second encoded data signal comprises an advanced data signal.

Abstract: A method for improving rate distortion performance of a compression system through parallel coefficient cancellation in a transform comprising the steps of (A) determining a block sum of absolute values for each of a plurality of blocks in a macroblock and (B) setting one or more coefficient values of a block to zero in response to a block sum value of said block being less than a first predetermined threshold value.

Abstract: A varactor is formed with a semiconductor junction having a retrograde dopant concentration profile in a depletion region. The retrograde dopant concentration profile results in an approximately linear capacitance/voltage characteristic response of the varactor. The retrograde dopant concentration profile also enables a peak of the dopant concentration to function as a low resistance conductive path connecting to the varactor.

Abstract: A bonding pad structure having an electrically conductive capping layer. An electrically conductive first supporting layer having major orthogonal sides is disposed under the electrically conductive capping layer. The electrically conductive first supporting layer is configured as a sheet having slotted voids in a first direction. An electrically conductive second supporting layer having major orthogonal sides is disposed under the electrically conductive first supporting layer. The electrically conductive second supporting layer is configured as a sheet having slotted voids in a second direction. The first direction and the second direction are associated one with another by being disposed at a positive value and a negative value of an angle, where the angle is neither zero nor ninety degrees with respect to the major orthogonal sides of the electrically conductive first supporting layer and the electrically conductive second supporting layer.

Abstract: A method for fabricating a semiconductor package having a 2-layer substrate, which includes an array of solder balls, is disclosed. The method includes patterning signal traces on a top layer of the substrate and identifying groups of signal traces to isolate. According to the present invention, a grounded isolation trace is then patterned adjacent to one of the groups of traces to isolate the signal traces, thereby providing noise shielding. In a preferred embodiment, the grounded isolation trace is provided with multiple vias, rather than only one. In a further aspect of the present invention a row of solder balls is connected together and to ground to create a bottom-layer isolating ground trace to further reduce noise. The bottom-layer isolating ground trace may be connected to the top-layer isolating ground trace using a via.

Abstract: A packaged integrated circuit including a package substrate having electrical contacts for receiving an integrated circuit. The integrated circuit is electrically connected to the electrical contacts of the package substrate. A stiffener is mounted to the package substrate, where the stiffener has a non-orthogonal cut out in which the integrated circuit is disposed. The edges of the cut out are disposed at no greater a distance from the corners of the integrated circuit than they are from the sides of the integrated circuit.

Abstract: A stiffener for reinforcing a package integrated circuit. The stiffener includes a rigid planar element having a first surface for bonding to a package substrate. The rigid planar element forms a major interior aperture for receiving and surrounding an integrated circuit on all sides of the integrated circuit. The rigid planar element also forms a minor interior aperture for receiving and surrounding a secondary circuit structure on at least three sides of the secondary circuit structure. In this manner, the stiffener provides structural support to the integrated circuit package, which reduces and preferably eliminates twisting and warping of the substrate package as it heats and is subjected to other stresses.

Abstract: A system is provided for yield enhancement in programmable logic. The system includes first and second random combinational logic, first and second sets of IP logic blocks, and first and second BIST/MUX controllers. The first controller is electrically connected between the first logic and each of the blocks in the first set and electrically connected between each of the blocks in the first set and the second logic. The second controller is connected in the same manner with respect to the second set of blocks. The controllers are configured to test the blocks for functionality or non-functionality, to identify functional ones of the blocks and to provide electrical connections between a predetermined number of the functional blocks and the first and second logic.

Abstract: The present invention may provide a circuit generally having a plurality of addressable memory cells and an access control circuit. The access control circuit may be configured to intercept an access to a faulty cell of the plurality of addressable memory cells. The access control circuit may be further configured to redirect the access to a spare cell of the plurality of addressable memory cells.

Abstract: A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be configured to (i) load the first program directly from the multiported memory to program a codec function and (ii) generate a video output signal by performing the codec function on a video input signal using video data exchanged with the multiport memory.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: An improved error correction code process takes advantage of information available from a post processor. This information is a list of highly probable error event patterns and locations found by employing a list Viterbi or a set of matched filters on Viterbi data. This list of possible errors can be used by the error correction code decoder in an iterative process whenever the correction power of the error correction code decoder is exceeded. If the error correction code decoder cannot correct the data on its first unassisted try, an iterative process is employed which, in essence, modifies the data with potential errors identified from the list created by the post processor and tries the correction process over again. An algorithm may be employed to try each error singly or in combination with other errors. This iterative process continues until a correctable indication is given by the error correction code decoder algorithm.

Abstract: A signal testing implementation provides significant advantages over conventional signal testing techniques. According to an exemplary embodiment, an apparatus for enabling signal testing such as SCSI signal testing in a test configuration includes a portable cable environment having a plurality of cables exhibiting a plurality of lengths and impedances. A user can selectively connect any one of the cables between a host device such as a server and a target device such as a disk subsystem. Signal measurement connectors which are connectable to the portable cable environment may be provided. According to an embodiment, each of the signal measurement connectors includes one or more test measurement points to enable collection of signal testing results.