Abstract: A tool for designing an integrated circuit and semiconductor product that generates correct RTL for I/O buffer structures in consideration of the requirements of diffused configurable I/O blocks and/or I/O hardmacs of the product. Given either a slice description of a partially manufactured semiconductor product, a designer can generate the I/O resources of an application set. Then given an application set having a transistor fabric, and the diffused configurable I/O blocks and/or the I/O hardmacs, and a plurality of accompanying shells, the I/O generation tool herein automatically reads a database having the slice description and generates the I/O buffer structures from the transistor fabric. The I/O generation tool further conditions and integrates input from either or both customer having her/his own logic and requesting a specific semiconductor product or from IP cores with their preestablished logic.

Abstract: A method for designing an Application Specific Integrated Circuit (ASIC) structure on a semiconductor substrate, includes (a) defining a class of circuit designs, the class having a common design part shared within the class and a custom design part variable for individual designs in the class, (b) allocating a set of bottom layers and a set of top metal layers to implement the common design part, the allocated sets of bottom layers and top metal layers having a fixed pattern for the class, and (c) implementing the custom design part using metal layers above the allocated set of bottom layers and below the allocated set of top metal layers. The method may further includes characterizing the ASIC for the common design and using the fixed patterns of the allocated set of bottom layers and the allocated set of top metal layers.

Abstract: A shared resource manager circuit for use in conjunction with multiple processors to manage allocation and deallocation of a shared resource. The shared resource manager allocates and deallocates software resources for utilization by the processors in response to allocation and deallocation requests by the processors. The shared resource manager may include a bus arbitrator as required in a particular application for interfacing with a system bus coupled to the processors to provide mutual exclusion in access to the shared resource manager among the multiple processors. The shared resource manager may manage a memory block (FIFO queue) with multiple resource control blocks. A system may advantageously apply a plurality of shared resource managers coupled to a plurality of processors via a common interface bus. Each shared resource manager device may then be associated with management of one particular shared resource.

Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.

Abstract: A method for processing a transport stream is disclosed. The method generally comprises the steps of (A) parsing the transport stream to separate a transport packet, (B) generating a plurality of status items for the transport packet, (C) writing a relevant portion of the transport packet and the status items together in a memory and (D) reading the relevant portion of the transport packet and the status items from the memory for post-parsing processing of the transport packet based upon the status items.

Abstract: An apparatus comprising a processor, an interface circuit and a memory. The processor may be configured to operate at a first data rate in response to a first clock signal. The interface circuit may be configured to (i) operate in response to the first clock signal, and (ii) convert data received from the processor over a system bus from the first data rate to a second data rate. The memory may be (i) coupled to the interface circuit and (ii) configured to present/receive data to/from the system bus at the second data rate.

Abstract: A method of forming a gate structure in an integrated circuit on a substrate. A high k layer is formed on the substrate, and a gate electrode layer is formed on the high k layer. The gate electrode layer is the patterned. LDD regions are formed using an ion implantation process, thereby creating damaged portions of the high k layer. A first portion of the damaged portions of the high k layer are removed, thereby defining a gate structure, and leaving remaining portions of the damaged portions of the high k layer. Sidewall spacers are formed adjacent the gate structure. Source/drain regions are formed using an ion implantation process, thereby further damaging the remaining portions of the damaged portions of the high k layer. The remaining portions of the damaged portions of the high k layer are then removed.

Abstract: A method for leveling an exposure field of view at a peripheral edge of a substrate. The field of view is aligned to a first position at the peripheral edge of the substrate, where the field of view has an inner edge and an outer edge, relative to the peripheral edge of the substrate. Whole device patterns within the field of view are identified, and the alignment of the field of view is altered to a second position so as to place the outer edge of the field of view adjacent the whole device patterns within the field of view. Level measurement information from the field of view at the second position is acquired and stored. The field of view is realigned to the first position, and the substrate is leveled within the field of view at the first position using the level measurement information acquired from the field of view at the second position.

Abstract: In a computerized data storage system, when data is to be updated in a primary, or “base,” logical volume, a snapshot volume is formed from the base volume. The updates are then made to the snapshot volume, preferably while the base volume is still used to satisfy normal I/O (input/output) access requests. After the updating is complete, the snapshot volume is rolled back into the base volume. During the rollback, any remaining original data in the base volume and the updated data in either the base volume or snapshot volume are available for satisfying the normal I/O access requests. Thus, the updating appears to be instantaneous, since the entire updated data is immediately available upon starting the rollback.

Abstract: An apparatus for detecting a predetermined pattern of bits in a data bitstream includes a series of detecting elements (2-6), each detecting element in the series corresponding to a predetermined bit in the predetermined pattern. Each detecting element receives a data bit from the data bitstream (8), the corresponding predetermined bit in the predetermined pattern and an error signal from a previous detecting element in the series. The output of each detecting element is an error signal indicative of the number of mismatches between the data bit and the corresponding predetermined bit in the predetermined pattern, both in previous detecting elements in the series in previous clock cycles and in the current detecting element in the current clock cycle. The error signal of the final detecting element (6) of the series is coupled to a logic control element (18) for detecting that a maximum allowed level of mismatches has been detected.

Abstract: A storage subsystem architecture in which front-end (host interface) control is separated from back-end (disk array) control. A plurality of front-end controller devices (FECs) and a plurality of back-end controller devices (BECs) are provided and are interconnected using storage area networking (SAN) switching devices. Each FEC and BEC includes a SAN interface. In a first preferred embodiment, the SAN interface is an InfiniBand compliant communication medium with associated switching and bus components. Alternative embodiments include a SAN interface that is pair of PCI bus interfaces each connected to one of two PCI bus backplanes. In this configuration, the SAN switch is simply the passive PCI backplane. In a second alternative preferred embodiment, redundant pairs of active SAN switch components are provided and each FEC and BEC includes a SAN interface appropriate to the particular SAN switch component selected.

Abstract: The present invention is directed to a uniform airflow diffuser for utilization in a process chamber, such as a process chamber utilized in the manufacture of semiconductor chips. The uniform airflow diffuser is suitable for generating a back flow of air sufficient to cause the airflow to be distributed across the airflow diffuser. The resultant build-up in pressure in the plenum area may result in uniform airflow through a plurality of holes included in the airflow diffuser yielding substantially laminar airflow through the chamber.

Abstract: An apparatus comprising one or more drive portions and a controller. The one or more drive portions may each comprise one or more drives. The controller may be configured to map correctly correlating addresses to the one or more drives.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

Abstract: A multi-level redistribution layer trace reduces current crowding in solder bumps of an integrated circuit package. A multi-level redistribution layer trace for an integrated circuit die includes a redistribution layer trace formed on the integrated circuit die in each of a plurality of electrically conductive layers and an I/O pad formed at a termination of the redistribution layer trace so that the I/O pad extends through each of the plurality of electrically conductive layers to form an electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers. The redistribution layer trace may also be slotted to divide current flow horizontally at the electrical junction between the termination of the redistribution layer trace and the I/O pad in each of the plurality of electrically conductive layers.

Abstract: A method for product assembly control comprising the steps of assembling the product in response to one or more assembly steps, tracking completion of the assembly steps, where a next one of the assembly steps is not started until each prior one of the assembly steps is completed, and tracking components consumed while performing the assembly steps.

Abstract: An automated framework and methodology for the development, testing, validation, and documentation of the design of semiconductor products that culminates in the release of a design kit having a flow manager and flow file to actualize a methodology to design a semiconductor product. The flow framework and methodology receives a methodology and a technology description for the semiconductor product. Then the flow framework and methodology coordinates and tests flow files developed by flow developers using testcases from testcase developers, libraries from library developers and tools from tool from flow developers that may be constantly updated. When a flow file, a testcase, a library, and/or a tool is updated, added, or otherwise changed, ongoing regression testing is accomplished to update the correct flow file.

Abstract: A Gaussian noise is simulated by discrete analogue ri,j. A first parameter &agr; and pluralities of first and second integers i and j are selected. A plurality of points i,j are identified and a magnitude si,j is calculated for each point based on &agr;, i and j. The discrete analogue ri,j is based on a respective si,j.

Abstract: A method of displaying a net in a CAD layout for an integrated circuit chip includes steps for receiving a netlist of an integrated circuit design, displaying a CAD layout of the netlist, selecting a net segment in the CAD layout, and displaying a physical characteristics list of information items representative of physical characteristics of the net segment.

Abstract: The present invention is directed to a system and method for tuning retry performance of read requests of data from electronic data storage devices. In an aspect of the present invention, a method for performing a delayed read in an electronic data storage system having an initiator and a target device may include initiating a delayed read by the initiator to the target device and issuing at least one delayed read. The initiator then delays for a programmed interval before reissuing the at least one delayed read.