Abstract: A packaged circuit with VDDcore contacts in first positions and VSScore contacts in second positions. A redistribution layer is adjacent the integrated circuit, and overlies VDDcore and VSScore mesh layers. First contacts in the redistribution layer are positioned in alignment with the first positions, to make connections between the redistribution layer and the VDDcore contacts. Second contacts are positioned in alignment with the second positions, to make connections between the redistribution layer and the VSScore contacts. First vias are positioned in alignment with the first positions, to make connections between the first contacts and the VDD mesh layer. The traces of the VDD mesh layer are positioned in alignment with the first positions. Second vias are positioned in alignment with the second positions to make connections between the second contacts and the VSS mesh layer. The traces of the VSS mesh layer are positioned in alignment with the second positions.

Abstract: The present invention provides systems and methods for logging information regarding write operations directed to the disk being upgraded while the single disk is inoperable during the upgrade process. When the upgrade of the disk is complete, the logged information is used to update the information stored on the upgraded disk. The logged information is sufficient to update the disk contents without requiring a time consuming total reconstruction of the entire content of the disk. In one exemplary preferred embodiment, the logged information identifies a logical block numbers of the disk that are impacted by write operations processed while the disk firmware was being upgraded. Only the data corresponding to the logged logical block numbers needs be reconstructed from the redundant data on other disks of the array. This method of data reconstruction is a less time consuming process than a total reconstruction of all data on the upgraded disk.

Abstract: Creation and detection of synchronization marks for a multilevel data storage medium is disclosed. A sequence of symbols is generated and the sequence of symbols is written to the multilevel data storage medium. A corresponding sequence may be generated by a detector and correlated with read data to detect the synchronization mark.

Abstract: Low resistance interconnect lines and methods for fabricating them are described herein. IC fabrication processes are used to create interconnect lines of Al and Cu layers. The Cu layer is thinner than in the known art, but in combination with the Al layer, the aggregate Cu/Al resistance is lowered to a point where it is comparable to that of a very thick Cu layer, without the additional cost and yield problems caused by using a thicker Cu deposition. Fuses for memory repair can also be fabricated using the methods taught by the present invention with only small variations in the process.

Abstract: A method for resource notification is disclosed. The method generally comprises the steps of (A) buffering a plurality of messages received from a plurality of busses, (B) arbitrating among the messages, (C) writing the messages in response to the arbitration, and (D) generating a plurality of notification signals on a plurality of lines in response to the messages as written to a plurality of addresses.

Abstract: The present invention is directed to a system and method of providing an integrated dynamic multipathing filter. A method of providing a data transfer between a host and a target in a network environment may include providing a logical identifier table by an input/output interface. The logical identifier table includes at least one logical identifier suitable for referencing a physical address identifier of a target. Communications between the host and the target are managed by selecting a route by the input/output interface from at least two routes associated with a logical identifier, the at least two routes communicatively coupling the input/output interface to the target so that the host may access the target utilizing the logical identifier.

Abstract: For use in an instruction queue having a plurality of instruction slots, a mechanism for queueing and retiring instructions. In one embodiment, the mechanism includes a plurality of tag fields corresponding to the plurality of instruction slots, and control logic, coupled to the tag fields, that assigns tags to the tag fields to denote an order of instructions in the instruction slots. In addition, the mechanism includes a tag multiplexer, coupled to the control logic, that changes the order by reassigning only the tags.

Abstract: The present invention is directed to a host interface bypass on a fabric based array controller. An apparatus of the present invention may include an external electronic device suitable for performing a function, a controller and a fabric connection. The controller includes at least one internal module, the internal module providing a controller function. The fabric connection communicatively connects the external device to the controller, wherein the module of the controller is directly accessible by the external electronic device.

Abstract: Growth of multiple gate oxides. By implanting different sites of a wafer with different doses of an oxide growth retardant, the entire wafer can grow oxides of different thicknesses even after being exposed to the same oxidation environment. The process is modular insofar as the implantation of one site has no effect on rate of growth of other sites.

Abstract: The present invention is directed to an optical proximity correction driven hierarchy. A method for constructing a hierarchy of optically independent structures for use in optical proximity correction of a circuit may include receiving an integrated circuit design, the design including geometric circuit elements for providing circuit functions of an integrated circuit. At least a portion of the integrated circuit design is exploded and geometric circuit elements of the exploded integrated circuit design are gathered into optically independent classes. A search is then performed for congruency for each optically independent class.

Abstract: A transmitter circuit improves a noise margin for decoding a common mode signal at a receiver circuit. The transmitter circuit includes a common mode signal transmitter and a noise margin enhancement circuit coupled to a transmission line. The common mode signal transmitter transmits a control message using a common mode signal. The common mode signal has a first voltage level and a second voltage level higher than the first voltage level, and the control message corresponds to a portion of the common mode signal having the first voltage level. The noise margin enhancement circuit raises a voltage level of the common mode signal to a third voltage level higher than the second voltage level for a specific time period from a rising edge of the common mode signal from the first voltage level.

Abstract: A method for providing sequential initialization of redundancy data in a volume comprising the steps of: (A) defining a boundary; (B) determining a location of the data with respect to the boundary; and (C) initializing a redundancy location of the volume and writing the data and a redundancy of the data to the volume.

Abstract: Provided is a process for forming a barrier film to prevent resist poisoning in a semiconductor device by depositing a second nitrogen-free barrier layer on top of a first barrier layer containing nitrogen. A low-k dielectric layer is formed over the second barrier layer. This technique maintains the low electrical leakage characteristics of the first barrier layer and reduces nitrogen poisoning of a photoresist layer subsequently applied.

Abstract: A method of operating a circuit is disclosed. The method generally comprises the steps of (A) generating a particular policy of a plurality of policies by a lookup operation on a first transaction request received by the circuit, (B) generating a second transaction request for use by a memory external to the circuit based upon the first transaction request and the particular policy in response to a first cache signal of the first transaction request having a non-cacheable state and (C) searching a plurality of address tags for cache data cached within the circuit for a match with the first transaction request in response to the first cache signal having a cacheable state.

Abstract: A process for measuring alignment of latent images in a photoresist layer of an integrated circuit structure on a semiconductor substrate with a test pattern formed in a lower layer on the substrate comprises the steps of forming a test pattern in selected fields of a first layer on a semiconductor substrate, forming a layer of photoresist over the first layer, forming latent images in portions of the photoresist layer lying in the selected fields overlying the test pattern of the first layer; and measuring the alignment of the test pattern in the selected fields of the first layer with the overlying latent images in the photoresist layer using scatterometry.

Abstract: A process of optimizing setup and hold time violations comprising resynthesis of data and clock logics coupled to pins of the integrated circuit to optimize setup time violations, and resynthesizing data and clock logics coupled to pins of the integrated circuit to optimize hold time violations. Optimization of setup time violations is performed by resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations, then resynthesis of the data logics of each pin having a setup time violation to optimize the setup time violations, and then resynthesis of the clock logics of each pin having a setup time violation to optimize the setup time violations. The hold time violations are then optimized by resynthesizing the data logics to optimize the hold time violations, and then resynthesizing the clock logics to optimize the hold time violations.

Abstract: A video decoder for decoding video pictures encoded according to the MPEG-2 standard, having reduced memory requirements, including a memory for storing means for storing a plurality of anchor frames, the decoder employing such anchor frames to generate B-frames, and including block-to-raster buffer means for holding B-frame data for display, the decoder being operable in first and second modes of operation, wherein in a first mode of operation a picture is encoded as a single frame and the video decoder decodes the entire frame twice wherein in a first decoding a set of lines of a first field are provided to the buffer for display, whereas in a second decoding lines from a second field are provided to the buffer for display; and wherein in a second mode of operation in which two consecutive field pictures of a frame are decoded, a first field picture is decoded and provided to the buffer means for display, and then a second field picture is decoded and provided to the buffer means for display.

Abstract: A clock generating circuit for a pseudo dual port memory incorporates feedback, delays, and latches to ensure that the write (read) operation clock pulse is sufficiently spaced in time from the read (write) operation clock. The clock generating circuit receives an external clock, a read enable signal, a write enable signal, and a reset signal as inputs. Advantages include minimization of the clock cycle time and operation unaffected by the duty ratio of an external clock. Delay circuitry may be added such that the generated clock signal has sufficient fan out and is sufficiently stable.

Abstract: An application specific integrated circuit, ASIC, having an advanced high-speed bus, AHB, operating in Advanced Microcontroller Bus Architecture, AMBA, and a bridge for connecting to an off-chip device is disclosed. The bridge includes a logical section and a buffer section for modifying AMBA signals to accommodate the differing clock speeds, voltages and signals required by the off-chip device. The logic section includes clock division and registers to store variables identifying the off-chip device and data being transferred from the AHB to the off-chip device. The buffer section provides any conversion of signal voltage levels between the core ASIC voltages and the input/output voltages required by the off-chip device.

Abstract: A message-based I/O architecture comprising a list describing one or more source buffers and a message header. The list may be segmented in multiple memory locations. The message header may be configured to (i) indicate whether the list is segmented and (ii) provide information for linking the list when the list is segmented.