Abstract: A dielectric film block is used in semiconductor processing to protect selected areas of the wafer from silicidation. The selected areas may include resistors. A first layer of oxide is formed on the resistor and a second layer comprising SiON or Si3N4 is disposed on the oxide. A mask is patterned to allow etching to take place in the areas where silicide formation is desired. The oxide layer serves as an etch stop layer during etching of the second layer.

Abstract: A package substrate having separate routing layers for transmitter signals and receiver signals, which signals are routed in differential pairs. The differential pairs of signal routing lines are isolated between a separate ground plane for transmitter and receiver traces and dedicated power planes, where a single power plane is dedicated to a single differential pair of signal routing lines. In this manner, a high degree of electrical isolation exists not only between the transmitter signal traces and the receiver signal traces, which are on different layers, but also between different differential pairs of signal routing lines on the same layer, each of which has its own dedicated power plane. Thus, a very high speed core routing system can be designed in a package substrate that can then be adapted as necessary to support a broad range of different integrated circuit designs.

Abstract: An integrated circuit with a power and ground distribution system having a first conductive layer, a second conductive layer, and an insulating layer disposed between the first layer and the second layer. A first ring is formed in the first layer, where the first ring forms a first loop around a peripheral portion of the integrated circuit. First straps are formed in the first layer, where the first straps have connections to the first ring. First horizontal members are formed in the first layer, where the first horizontal members have connections to the first ring. Second horizontal members are formed in the first layer, where the second horizontal members do not have connections to the first ring. A second ring is formed in the second layer, where the second ring forms a second loop around the peripheral portion of the integrated circuit. The second ring is interleaved with the first ring. Second straps are formed in the second layer, where the second straps have connections to the second ring.

Abstract: The present invention is directed to an improved method for the binarization of data in an MPEG data stream. The invention makes use of unary binarization to create codewords up until an index threshold. Once the threshold has been met, succeeding code symbols have appended to them an exp-Golomb suffix. This hybrid binarization scheme reduces the number of binary codewords to be processed by a Binary Arithmetic Coder (BAC), thus reducing the computation required by the BAC.

Abstract: A tool and method for increasing fault coverage of an integrated circuit. The tool includes a key nodes detection device for matching key nodes to a fault grading report list of undetected nodes, a multi-sites selection device for reading a layout file of available multi unit sites for the integrated circuit, a site matching device for matching available multi-unit sites to key undetected nodes, and a netlist generation device for building logic functions in the available multi-unit sites for connection to the key undetected nodes. Use of the invention enables increased fault coverage of integrated circuit circuits for little or no added expense.

Abstract: An integrated circuit, including a substrate with circuitry formed therein, where the substrate has a peripheral edge. Also included are a top most electrically conductive layer and an underlying electrically conductive layer. Outer bonding pads are disposed in an outer ring, and are formed within the top most layer. Inner bonding pads are disposed in an inner ring, and are formed within the top most layer. Inner connectors electrically connect the inner bonding pads to the circuitry. The inner connectors are formed within the underlying layer, and have a width that is less than the width of the inner bonding pads, thereby defining a gap between the inner connectors. Outer connectors electrically connect the outer bonding pads to the circuitry. The outer connectors are formed within the underlying layer, and have a width that is less than the width of the gap between the inner connectors.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: An apparatus and method for storing image data comprising a first storage device and a second storage device. The first storage device may be configured to store at least one first pixel from a first field of a frame of the image at a first physical address in the first storage device. The second storage device may be configured to store a second pixel from a second field of the frame of the image at a second physical address in the second storage device. The first and second physical addresses may have the same relative position in an address space of the respective storage devices.

Abstract: An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.

Abstract: An apparatus comprising a data modification circuit and a composite circuit. The data modification circuit may be configured to generate a first and second video component in response to a video data stream. The composite circuit may be configured to present an output graphics stream by interleaving the first and the second video component.

Abstract: Circuits and associated methods for operation thereof for gathering real-time statistical information regarding operation of the arbiter circuit in a particular system application. The real-time statistical information so gathered is useful for off-line analysis by a system designer for determining optimal configuration and parameter values associated with operation of a particular arbiter in a specific system application. In a first exemplary preferred embodiment, a timer circuit associated with the arbiter measures a predetermined period of time during which statistical data is to be gathered. Counter circuits associated with the arbiter count the number of occurrences of events of interest to the designer during the time period measured by the timer circuit. Each counter circuit preferably senses and counts a particular event of interest to the designer.

Abstract: According to one embodiment, a method of planarizing of a surface of a semiconductor substrate is provided. A copper layer is inlaid in a dielectric layer of the substrate. The semiconductor substrate is disposed opposite to a polishing pad and relative movement provided between the pad and the substrate. An electrolytic slurry containing abrasive particles is flowed over the substrate or the pad. A voltage is applied between the polishing pad and the substrate to perform electropolishing of the substrate. The rate of chemical mechanical polishing is controlled by the down force applied to a polishing head urging the substrate against the polishing pad.

Abstract: Methods and structure for improving accuracy of a master delay line associated with slave delay lines wherein the master delay line is design utilizing a higher clock frequency then the clock frequency applied to associated slave delay lines. The higher clock frequency applied to the master delay line in accordance with the present invention permits the master delay line to be comprised of fewer delay elements than would be the case for a master delay line using the same basic clock frequency as associated slave delay lines. The lower number of delay elements comprising the master delay line (i.e., the shorter length of the master delay line) helps reduce static phase errors associated with the master delay line inherent in the design, layout and fabrication of a longer delay line.

Abstract: A communications receiver and method are provided for receiving a transmitted signal from a transmission channel having a low-pass filter characteristic. The receiver includes a receiver input for coupling to the channel and a switched capacitor pre-emphasis filter coupled to the receiver input. An analog-to-digital (A/D) converter is coupled to an output of the pre-emphasis filter. An equalizer is coupled to an output of the analog-to-digital converter.

Abstract: A counter stage generally comprises a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.

Abstract: An apparatus having a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first phase control signal in response to a phase difference between a first input clock signal and a first output clock signal. The second circuit may be configured to generate a second phase control signal in response to a phase adjust signal. The third circuit may be configured to generate the first output clock signal by delaying the first input clock signal in response to a delay control signal. The delay control signal may be generated by summing the first and the second phase control signals.

Abstract: An improved method and design for adjusting clock skew in a wire trace is disclosed. Aspects of the invention include a corrugated pattern wire trace bracketed by a pair of parallel conducting wire frames with wire extensions projecting between the corrugations of the wire trace. The wire frames are connected to a voltage supply. The transmission properties of the wire trace, and thus the degree of clock skew associated with the wire trace, are affected by the number of wire extensions protruding between the corrugations, their degree of penetration, as well as other factors inherent in the design. The present design can achieve the same degree of clock skew with a smaller surface area covered and with fewer resistive losses than with prior art designs.

Abstract: An apparatus comprising a first stage and a second stage. The first stage may have a first plurality of states connected by a first topology. The second stage may have a second plurality of states connected by a second topology. The second topology may be different from the first topology.

Abstract: A method and composition for a composite spacer with low overlapped capacitance includes a low-k dielectric spacer layer. A first spacer is deposited on a partially formed semiconductor device having a gate oxide stack, followed by a low dielectric constant spacer layer. Anisotropic etching of the combined layers form spacers surrounding the gate oxide stack.

Abstract: A method of forming an electrically conductive structure on a substrate. An electrically conductive electrode layer is formed on the substrate, and an electrically conductive conduction layer is formed over the electrode layer. The conduction layer is formed by placing the substrate in a plating solution. A first current is applied to the substrate at a first bias and a first density for a first duration. A second current is applied to the substrate at a second bias and a second density for a second duration. The first current and the second current are cyclically applied at a frequency of between about thirty hertz and about one hundred and thirty hertz.