Abstract: A circuit generally comprising a memory and a core module is disclosed. The memory may be configured as (i) a first stack having a plurality of index pointers and (ii) a table having a plurality of entries. The core module may be configured to (i) pop a first index pointer of the index pointers from the first stack in response to receiving a first command generated by a first module external to the circuit, (ii) assign a first entry of the entries identified by the first index pointer to the first module, (iii) generate an address in response to converting the first index pointer and (iv) transfer the address to the first module.

Abstract: A method for motion estimating is disclosed. The method generally comprises the steps of (A) generating a first interpolated block having a sub-pixel resolution in response to a first interpolation process operating on a reference block of a reference frame of a video signal having an integer pixel resolution, (B) generating a motion vector in response to the first interpolated block and a current block of a current frame of the video signal having the integer pixel resolution and (C) generating a second interpolated block having the sub-pixel resolution in response to a second interpolation process operating on the reference block.

Abstract: A networking/communication chip having a receiving buffer or FIFO whereby it receives data from a data source across a network and transfers the data to a host system. The memory in the host system acts as a logical extension of the receiving buffer in the chip; in this way, the host system controls the flow of data from the source, rather than the control flow being based on the capacity of the receiving buffer in the networking/communication chip. The networking/communication chip may be a controller, such as a 10 Gigabit Ethernet controller, wherein data received from the source in one protocol is transformed to a second protocol input to the host. If either or both the networking/communication chip or the host system is/are made of FPGAs, it/they can be reprogrammed to disable the flow control in the networking/communication chip and enable flow control in the host system. Data flow is enhanced because memory in the host system typically is much larger than memory in the networking/communication chip.

Abstract: A method for determining an end point of a planarization process for removing metal from a surface of a substrate submerged in an electrolytic solution or slurry. A first electrode is provided which is operable to contact the surface of the substrate, such as a working electrode of a potentiostat system. A second electrode is provided which is operable to contact the electrolytic solution, such as a reference electrode of the potentiostat system. The first electrode is contacted to the surface of the substrate and an electrochemical property is measured, such as the electrochemical potential between the first and second electrodes, where the electrochemical property is indicative of an electrochemical characteristic of the substrate-slurry system. The planarization process is preferably stopped when a substantial change in the electrochemical potential of the system is measured.

Abstract: A platen for use in a dry etching process for substrate production, the platen having a surface susceptible to chipping and/or particle generation from the dry etching process and a coating applied to at least a portion of the surface for rendering the surface less susceptible to chipping and/or particle generation, the coating comprising a silicon carbide coating.

Abstract: A plurality of devices communicate information over a wireless network at radio frequencies. The information includes digital audio, video and data. Bandwidth among the devices is dynamically allocated, the allocation being based upon the needs of the devices. One embodiment of the wireless network is a Time Division Multiple Access network. Another embodiment is a wireless Ethernet. Yet another embodiment is a Frequency Division Multiplexed network.

Abstract: A chemical vapor deposition process controls the thickness of a film on an edge of a wafer by modifying the density of flow gases at the edge of the wafer through the use of a gas flow control ring. The deposition process is performed with the gas flow control ring disposed about a wafer holding region on a wafer holder. The top surface of the gas flow control ring is controlled relative to the top surface of the wafer to adjust the thickness of the film deposited on the wafer edge. In one particular embodiment, the gas flow control ring has a top surface in the same plane as the top surface of the wafer. In another embodiment, the deposition process is performed with the clearance between the inner diameter of the gas flow control ring and the periphery of the wafer minimized.

Abstract: The present invention is directed to a method and system for automating data storage array components testing. A serial number of a data storage array component (i.e., product) is used to determine if the product is of high priority (rank) in comparison with other products in a queue and there is any test cell available for testing the product. Next, if a test is required, the product type and test requirements of the product are retrieved from a database based on the serial number, and the product is routed to the test cell from an assembly line. Then the product and a storage component interface module of the test cell are positioned so that the product and the storage component interface module face each other. The storage component interface module is chosen based on the test requirements retrieved from the database. Next the product is docked into the storage component interface so that the product is connected to the storage component interface module. Then the test is run to completion.

Abstract: A method for improving bandwidth utilization in a packet-switched network via real time control of pause frame transmissions. The invention provides a mechanism whereby a pause frame may be effectively negated if, during the transmission of the pause frame, the network conditions necessitating the pause frame are eliminated or abated. In one Ethernet-compliant embodiment of the invention, monitoring circuitry is provided in a network device to ascertain changes in flow control conditions. Following detection of a flow control condition (e.g., a transmit buffer overflow condition), a flow control unit in the network device initiates transmission of a pause frame. Typically, the initial pause time value will be set to a maximum value (e.g., “FFFF”). During or immediately prior to transmission of the pause frame, the monitoring circuitry functions to monitor the state of the flow control unit or flow control enablement signals to determine if the flow control condition remains in effect.

Abstract: An array controller of a data storage system initiates a test of another array controller of the data storage system to determine the operational condition of the controller under test (CUT) as well as an array of storage devices to which the CUT is connected and a network fabric over which the CUT receives commands from host devices of the data storage system. If the CUT or devices connected thereto are not functioning properly, the controller initiating the test can diagnose the problem. The controller initiating the test instructs the CUT to perform certain normal operating functions, e.g. data read and write functions, and checks whether the functions are completed correctly. Additionally, a loopback test checks the operation of the network fabric, and the read and write functions also check the operation of the storage devices.

Abstract: A tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit. Given a manufactured slice that has a number of blocks already diffused and logically integrated, the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer's requirements for memory. The memory generation tool has a memory manager, a memory resource database, a memory resource selector, and a memory composer. Together these all interact to generate memories from the available memories within the memory resource database. The memory composer actually generates the RTL logic shells for the memories, and outputs the memory designs in Verilog, VHDL, or other tool synthesis language. Once a memory is created, it is tested.

Abstract: A method for creating a derivative semiconductor design layout is disclosed. The method generally comprises the steps of (A) receiving a plurality of changes from a user for a first layout of a semiconductor design having a plurality of first layers, (B) storing the changes in a plurality of second layers and (C) displaying the derivative semiconductor design layout to the user in response to logically operating on the first layers and the second layers.

Abstract: A partially manufactured semiconductor chip comprising a slice and a number of shells is a template for a communication and networking chip. The slice has a number of I/O ports, blocks, and PHYs. The hardmac PHYs are established to correspond to a high speed data transmission protocol. The interior of the template comprises logic gate arrays and configurable memory. Once particular protocols of data receipt and transmission are selected, the logic gate arrays and configurable memory can be programmed and otherwise configured to develop protocol layers for data networking and communication.

Abstract: A method, program and system for recovering data from a failed drive in a RAID system are provided. The invention comprises assigning a plurality of storage drives within the RAID to a defined volume group. If a failure of a drive in the volume group is detected, the failed drive is removed from the volume group, and data from the failed drive is redistributed to the drives remaining in the volume group. In another embodiment of the present invention, a previously unused drive in the RAID is assigned to the volume group to replace the failed drive, and the data on the failed drive is reconstructed on the newly assigned drive. In yet another embodiment, two or more previously unused drives are assigned to the volume group to replace each failed drive. The data from the failed drive is then re-striped across the remaining drives in the volume group, including the newly assigned drives.

Abstract: The present invention is directed to a system and method for disabling and recreating a snapshot volume. A method of disabling repository volume activity corresponding to a point-in-time image and retaining repository volume attributes may include initiating a command in a electronic data storage system. The command disables copy-on-write activity to a repository volume created in relation to a first point-in-time image of a base volume, in which repository volume attributes are retained suitable for providing a repository volume corresponding to a second point-in-time image. A method of creating a point-in-time image of a base volume may include initiating a command to create a second point-in-time image of a base volume. The second point-in-time image is created utilizing a repository volume having attributes retained from a repository volume created previously with respect to a first point-in-time image.

Abstract: An oscillator circuit includes an electrical load, a first metal oxide semiconductor (MOS) devise, a second MOS device, and a negative feedback circuit. The electrical load is coupled between a first node and a second node. The first MOS device is coupled between the first node and a third node, and controls a first current flowing from the first node to the third node. The second MOS device is coupled between the second node and a fourth node, and controls a second current flowing from the second node to the fourth node. A positive feedback circuit is formed with the first and second MOS devices. The positive feedback circuit has inputs from the first and second nodes and outputs to the first and second MOS devices. The negative feedback circuit has inputs from the third and fourth nodes and outs to the first and second MOS devices.

Abstract: A vortex unit suitable for providing a desired environment for a semiconductor process may include a vortex tube and a semiconductor processing device suitable for performing a semiconductor processing function. The vortex tube includes an air inlet for receiving compressed air, a first air exhaust for outputting an air stream having a temperature greater than the received compressed air, and a second air exhaust for outputting an air stream having a temperature lower than the received compressed air. The semiconductor processing device is connected to the second air exhaust of the vortex tube so that the semiconductor processing device receives a cooled air stream from the vortex tube, the cooled air stream providing an environment suitable for enabling the semiconductor processing device to perform the semiconductor processing function.

Abstract: The present invention is directed to a method of recovering a write ahead log after an interruption. In a first aspect of the present invention, a method of writing a log entry of a write ahead log may include initiating a log write to a write ahead log, the write ahead log having a first sector, and a second sector, wherein the first sector is followed by the second sector. A log entry including a sequence number is written to the second sector. Then, the log entry including the sequence number is written to the first sector.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-progrmnmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: An apparatus comprising a plurality of first counters, a second counter, and a logic circuit. The plurality of first counters may each be configured to increment a first value in response to receiving one of a plurality of incoming data packets on an associated port. The second counter may be configured to increment a second value in response to a highest value of said first values being incremented. The logic circuit may be configured to generate an output representing a volume of packet traffic in response to the plurality of first values and the second value. The output signal generally indicates which of a plurality of ports is best suited for implementing flow control.