Abstract: A method for composing memory on a programmable platform device comprising the steps of: (A) accepting information about a programmable platform device comprising one or more diffused memory regions and one or more gate array regions; (B) accepting predetermined design information for one or more memories; and (C) composing one or more memory building blocks (i) in the one or more diffused memory regions, (ii) in the one or more gate array regions or (iii) in both the diffused memory and the gate array regions based upon the predetermined design information and the information about the programmable platform device.

Abstract: A power supply feedthrough protection circuit which solves the problem of voltage feedthrough from a bus cable charging a chip power-supply beyond acceptable transistor limits. The circuit continuously senses the chip power-supply, compares the supply to an acceptable threshold, and provides a low-impedance current path as soon as the power-supply exceeds the threshold. The circuit allows a driver to draw current from the cable, in a controlled manner, and provides that the power supply is therefore never allowed to exceed the maximum allowable limit for transistors.

Abstract: Embodiments of the invention include a capping layer of alloy material formed over a copper-containing layer, the alloy configured to prevent diffusion of copper through the capping layer. In another embodiment the alloy capping layer is self-aligned to the underlying conducting layer. Specific embodiments include capping layers formed of alloys of copper with materials including but not limited to calcium, strontium, barium, and other alkaline earth metals, as well as materials from other groups, for example, cadmium or selenium. The invention also includes methods for forming an alloy capping layer on a copper-containing conducting structure. One such method includes providing a substrate having formed thereon electrically conducting layer comprised of a copper-containing material and forming an alloy capping layer on the electrically conducting layer. In another method embodiment, forming the alloy capping layer includes forming a self-aligned capping layer over the conducting layer.

Abstract: A method and apparatus for transmitting data in a node having a buffer. A first set of data is received in a buffer for transmission to a target node. The first set of data is sent to the target node. Responsive to an indication that the target node is unable to receive data, a second set of data is loaded into the buffer for transmission to another target node, while the first set of data is retained in the buffer.

Abstract: In a method of forming an integrated circuit device, sidewall oxides are formed by plasma oxidation on the patterned gate. This controls encroachment beneath a dielectric layer underlying the patterned gate. The patterned gate is oxidized using in-situ O2 plasma oxidation. The presence of the sidewall oxides minimizes encroachment under the gate edge.

Abstract: A method is provided for fabricating an integrated circuit having a logical function. The method includes fabricating first and second routing layer masks and a first via mask. The first routing layer mask includes power supply segments and signal segments. The second routing layer mask includes signal segments and filler segments, wherein the filler segments are located in unused areas of the second routing layer mask. The first via mask defines vias that electrically couple the filler segments to the power supply segments. If the logical function is changed after the masks have been fabricated, a second via mask is fabricated. The second via mask decouples a filler segment from the power supply segments and couples the filler segment to a signal segment defined by the first routing layer mask to implement the logical function change. The integrated circuit is then fabricated with the first and second routing layer masks and the second via mask.

Abstract: The present invention concerns an apparatus comprising a first plurality of contacts, a second plurality of contacts, one or more sockets, and a programmable processor. The first plurality of contacts may be configured to receive one or more first signals. The second plurality of contacts may be configured to present one or more second signals in response to the one or more first signals. The one or more sockets may be configured to receive one or more third signals from one or more programmable devices. The programmable processor may be configured to generate a test signal in response to (i) the one or more first signals and (ii) the one or more third signals.

Abstract: A substrate of the type for receiving an integrated circuit and a mold cover. The mold cover covers a first portion of the substrate and leaves a second portion of the substrate exposed with a boundary edge between the first portion of the substrate and a second portion of the substrate. The substrate has electrically conductive traces and electrically conductive vias on an upper layer adjacent the mold cover. The electrically conductive traces do not cross the boundary edge on the upper layer of the substrate.

Abstract: A method for fabricating buried channel NMOS devices and the devices themselves are disclosed. These buried channel NMOS devices are fabricated with a p-type substrate, an n-type implant in the top portion (approximately 400 to 1000 Å deep) of the substrate, and an insulating gate dielectric above the n-type implant. An n-type or p-type doped polysilicon gate electrode is formed on top of the insulating gate dielectric. The n-type implant region is doped in such a way that it is depleted of charge carriers when the device's gate electrode is at the same potential as the well (zero bias). When the gate electrode is biased +Ve with respect to the device's well substrate a conducting channel of mobile electrons is formed in a portion of the buried layer. This type of biasing is known as inversion bias since the charge carriers are of the opposite type than the p-well.

Abstract: An integrated circuit test apparatus and a method for testing an integrated circuit are described. The integrated circuit test apparatus includes a holder adapted to receive a wafer, where a frontside of the wafer is accessible to be probe tested by electrically conducting probe needles during which a backside of the wafer is accessible to be scanned by an optical scanning mechanism. The scanning mechanism can optically detect photoemission-generated defects resulting from electrical stimuli applied to the integrated circuits via the probe needles. The holder is coupled to a three-dimensional translational mechanism that will allow for automated multi-die test probing.

Abstract: The present invention is directed to a parallel/serial SCSI with legacy support. A small computer system interface (SCSI) converter module may include a small computer system interface (SCSI) converter. The converter is suitable for converting a parallel bus structure to a serial bus structure, and the converter is also suitable for supporting a parallel bus structure to a parallel bus structure.

Abstract: A rectangular termination ring for a power distribution mesh is placed on the upper two layers of an integrated circuit and may be placed over some I/O circuitry. The strapping connecting the bonding pads to the termination ring are placed on upper levels of the integrated circuit, minimizing the via requirements and freeing space for additional circuitry. Further, the termination ring may be adapted to work in conjunction with L-shaped, as well as other power distribution meshes.

Abstract: The present invention may provide a digital memory circuit comprising a plurality of multi-bit registers, a memory circuit interface, and a logic circuit. The memory circuit interface may be configured to access a selected one of the registers. The logic circuit may be coupled to the plurality of multi-bit registers and responsive to data received through the interface for selectively writing a predetermined logic state to at least one first bit of the selected register while leaving at least one second bit in the selected register with an unmodified state.

Abstract: A circular buffer control circuit, a method of controlling a circular buffer and a digital signal processor (DSP) incorporating the circuit or the method. In one embodiment, the circuit includes: (1) address calculation logic, having multiple datapaths, that calculates, from data regarding a buffer operation, an updated address result therefor and (2) modification order determination circuitry, coupled in parallel with the address calculation logic, that transmits a memory access request and the updated address result in an order that is based on whether the buffer operation is pre-modified or post-modified.

Abstract: A method for controlling arbitration that may be used for a bus. The method generally comprises the steps of (A) controlling a bus mastership for the bus using a first arbitration scheme, (B) controlling the bus mastership using a second arbitration scheme in response to a first signal indicating a delay in a transfer between a first master of a plurality of masters and a slave on the bus, and (C) controlling the bus mastership using the first arbitration scheme in response to a second signal ending the delay in the transfer between the first master and the slave.

Abstract: A method of forming a layer over a substrate is provided. Generally, a layer of a first reactive species is deposited over the substrate. The layer of the first reactive species is reacted with a second reactive species to create a first product. Unreacted reactive species is preferentially desorbed leaving a layer of the first product.

Abstract: A method for forming an active area in a substrate includes the steps of growing an isolation oxide on a silicon substrate, providing a photresist mask to define the active areas on the substrate, performing etching and stripping processes, removing the residual oxide from the active areas and selectively growing an epitaxial silicon layer.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be conf igured to generate an address signal in response to (i) a first ramp signal, (ii) a second ramp signal, and (iii) a format signal. The second circuit may be configured to generate the first and second ramp signals in response to a one or more control signals. The address signal may support a raster format when the format signal is in a first state and may support a macroblock format when the format signal is in a second state.

Abstract: Electrical components and associated processes for enhancing automated test of a system by permitting automated generation and application (injection) of real-world stimuli applied to the system under test without the need for manual intervention. Electrical components of the present invention intercede in the exchange of signals and power over various signaling paths within a system under test. Under programmable control by methods of the invention, the electrical components of the present invention may simulate any desired real-world stimulus on any signal path associated with the system under test. Automated test procedures associated with the electrical components may then automate all phases of a test procedure including setup of the test environment, application of real-world stimuli, verification of operation of the system under test and cleanup and recovery following performance of the automated test sequence.

Abstract: The subject matter described herein involves an improved etch process for use in fabricating integrated circuits on semiconductor wafers. The selectivity of the etch process for silicon carbide versus silicon oxide, organo silica-glass or other low dielectric constant type material is enhanced by adding hydrogen (H2) or ammonia (NH3) or other hydrogen-containing gas to the etch chemistry.