Abstract: A method and system for controlling and normalizing a rate of a process is described. A hidden process is executed a predetermined number of times as a loop value, and a visual process is executed to complete a cycle. The time to complete a cycle is measured, and an updated loop value is calculated. In a subsequent cycle, the hidden process is executed a number of times equal to the updated loop value so that the visual process is executed at a desired rate normalized across all computing platforms, configuration, and performance environments. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other researcher to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).

Abstract: A conditioning bar assembly includes a polycarbonate member, an abrasion member, and a rigid metal element. The abrasion member is supported on an outer surface of the polycarbonate member. The rigid metal element is supported on the polycarbonate member, at least a portion of the polycarbonate member disposed between the rigid metal element and at least a portion of the abrasion member.

Abstract: A computer readable medium encoded with instructions for executing the steps of: receiving information about a driving cell from a layout tool, receiving information about an interconnect from a layout tool, determining buffer cell information based upon information about the driving cell and the interconnect by accessing a previously defined library lookup table, relaying the buffer cell information from the library look up table to the layout tool.

Abstract: The present invention provides a field programmable universal serial bus application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the field programmable universal serial bus application specific integrated circuit includes a universal serial bus function core configured to transmit and receive data via a universal serial bus and a programmable logic core having an array of dynamically configurable arithmetic logic units. The programmable logic core is configured to interface with the universal serial bus function core and implement at least one application level function capable of performing protocol conversion to at least one processor bus protocol.

Abstract: A method for isolating SAN Fibre Channel faults in both laboratory and customer site environments, thereby reducing or eliminating uncertainty typically involved in isolating faulty components and decreasing fault isolation time is disclosed. The method provides multiple levels of analysis including providing diagnostic information for a component within the SAN Fibre Channel environment, the diagnostic information being suitable for indicating a fault of the component; analyzing the diagnostic information for determining a cause of a fault indicated by the diagnostic information; and furnishing a possible cause of the fault indicated by the diagnostic information based on analysis of the provided diagnostic information. In exemplary embodiments, the method may be implemented by a Fibre Channel fault isolator coupled to the SAN.

Abstract: A method to improve the resolution of a photolithography system by using one or more coupling layers between a photo resist and an anti-reflective coating. The coupling layer(s) compensate for a mis-match in indexes of reflection between the photo resist and anti-reflective coating and minimize the amount of energy which is reflected back into the photo resist, thereby improving the quality of the resulting image which is formed on the photo resist during the process.

Abstract: The present invention is directed to a composition with electromagnetic compatibility (EMC) characteristics. In an aspect of the present invention, an adhesive suitable to provide a bond between components may include an adhering material suitable for holding a first surface and a second surface in contact. A plurality of items is disposed in the adhering material. The plurality of items has electromagnetic capability shielding characteristics.

Abstract: A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n−1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n−1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.

Abstract: A segmented computer network topology has a plurality of network hosts, which are coupled in a ring. A method of resetting the segmented computer network topology includes initiating a reset sequence having a flushing phase, a subsequent scrubber selection phase, a next subsequent slot identification phase and a next subsequent ring start-up phase. Selected packets received by the network hosts are flushed from the ring during the flushing phase. A single one of the network hosts is selected as a scrubber host during the scrubber selection phase. A unique slot identifier is assigned to each of the network hosts during the slot identification phase. A ring start-up packet is sent from the scrubber host to each of the other network hosts over the ring during the ring start-up phase.

Abstract: A method of determining interrupts in data on an optical disc, the data supported in a signal envelope subject to variation by mirror modulation and said interrupts. The method comprises the steps of (A) filtering the signal envelope to generate a first signal; (B) re-biasing the first signal to produce an intermediate signal having voltage swings attributable to the mirror modulation; (C) defining a slice level below a reference level to sample the mirror modulation to produce a mirror signal; (D) slicing the intermediate signal to generate the mirror signal containing a pulse resulting from a level transition through the slice level associated with re-biasing of the positive transition component; and (E) registering the presence of the pulse during the on-track mode of operation to identify the interrupt in data on the optical disc.

Abstract: An apparatus comprising a transmit data path, a receive data path, a first circuit and a second circuit. The first circuit may be configured to transfer data between a first interface and the transmit and receive data paths. The second circuit may be configured (i) to transfer the data between the transmit and receive data paths and a second interface and (ii) to control a configuration update of the first and second circuits in response to a plurality of control signals. The configuration of the first and second circuits is generally dynamically updated.

Abstract: A method and an architecture for recovery from a branch misprediction in a processor. The method may include the steps of (A) evaluating a branch prediction for a branch instruction, (B) pausing an instruction cache line fetch in response to the branch instruction, and (C) resuming the instruction cache line fetch from where paused in response to evaluating the branch prediction as incorrect to recover from the branch misprediction.

Abstract: A process for etching oxide is disclosed wherein a reproducibly accurate and uniform amount of silicon oxide can be removed from a surface of an oxide previously formed over a semiconductor substrate by exposing the oxide to a nitrogen plasma in an etch chamber while applying an rf bias to a substrate support on which the substrate is supported in the etch chamber. The thickness of the oxide removed in a given period of time may be changed by changing the amount of rf bias applied to the substrate through the substrate support.

Abstract: A built-in self test implementation for testing the speed and timing margins of the IO pins of a source synchronous IO interface (SSIO). The implementation preferably includes built-in self test logic including a pseudo-random pattern generator which is configured to generate input sequences. Buffers are connected to the IO pins, and the buffers are configured to receive the input sequences. The buffers are connected to multiple input signature registers, and the multiple input signature registers are configured to receive the input sequences from the pseudo-random pattern generator and generate signatures. Comparators are provided to compare the signatures to expected vector values and generate a pass/fail output signal. Preferably, at least one programmable delay cell is disposed between each buffer and the multiple input signature registers. The programmable delay cells provide that propagation delays can be set to perform timing margin tests.

Abstract: The present invention provides a characteristic impedance equalizer and method of manufacture thereof for use with an integrated circuit package having first and second signal transmission zones. In one embodiment, the characteristic impedancs equalizer includes a first conductor having a first width and providing a characteristic impedance within the first signal transmission zone. The characteristic impedance equalizer also includes a second conductor, coupled to the first conductor, having a second width and providing substantially the same characteristic impedance within the second signal transmission zone.

Abstract: A bus interface and a receiver in the bus interface receive signals from a computer bus, such as a SCSI (Small Computer System Interface) bus, and deskew and synchronize the signals into valid data and control signals. The signals are aligned and then a portion of the signals is offset to ensure that the other signals have sufficient time to stabilize before being latched. The alignment is performed by adding and subtracting delay units to and from the signals. The offset is determined by a self-calibration logic that uses the same type of delay units.

Abstract: A bus is defined on a core of an integrated circuit. Routing lines are defined through the core, and net wires are routed through the core along respective routing lines. Buffer columns are defined in the core across a plurality of nets, and buffers are placed in the buffer columns so that an input and output to a respective buffer are on different routing lines. The buffers have at least one free routing line and the net wires are redistribution across the buffer so that (i) the net wire to be buffered is re-routed to the input and output of the buffer, (ii) the net wires on routing lines containing the input and output of the buffer are re-routed to the routing line of the net wire to be buffered and the free routing line, and (iii) all other net wires are routed along their respective routing lines.

Abstract: Methods and structure for loading a CRC value cache memory in a storage controller on the fly to reduce overhead processing associated with access to system memory to load the CRC value cache memory. The invention provides for circuits and methods for monitoring normal system accesses to system memory to manipulate CRC values in system memory in conjunction with associated access to disk drive of a storage subsystem. When accesses are detected loading or retrieving CRC values from system memory, the CRC values are loaded substantially in parallel into the CRC value cache memory.

Abstract: A method for augmenting the memory capabilities of an option ROM in which PCI function calls are used to access a larger sized non-volatile memory. Thirty two bit addressing is used in the PCI function call routines to allow for 4 GB addressing. An option ROM and the separate larger sized non-volatile memory or a single non-volatile memory may be used for storing the overflow images.

Abstract: A fixture is used to secure a substrate and to allow movement of a pin relative ot the fixture. The substrate fixture includes a holding table adapted to receive the substrate and a probe pin assembly underneath the table. The substrate is mounted on a table which can move in one-dimension, while the probe pin is moveable relative to the table in another dimension perpendicular to movement of the table. Moving the substrate retaining table and the pin retainer allows for alignment of the probe pin with a backside terminal of a trace conductor of the substrate. The assembly also has vertical height translational mechanism for contacting the probe pin with the backside terminal. Furthermore, the frontside terminal of the trace conductor is accessible to an external probe. A testing device can be connected to the external probe and the probe pin to measure the electrical continuity of the trace conductor.