Abstract: The present invention is directed to a system for providing a removable access panel for utilization with electronic devices. The panel of the present invention is connected to the frame of an electronic device through the use of a pocket hinge which allows a curved extension on the cover to engage a corresponding curved surface included in the pocket. Utilization of the present invention allows for the electronic device to maintain its overall provide while providing a hinge system allowing for ease of access and removable functionality.

Abstract: The present invention allows a user to draw a closed periphery around an amount of information on the display of a pen-based computer system. The periphery information is transmitted to the computer system by a digitizing tablet. When received by the computer system, the computer system divides the area enclosed by the periphery into a number of lines. The computer system then processes each of these lines and determines the information to erase on a given line.

Abstract: A system for automatically migrating a portion of a collection of information located on source data carrier(s) into an assemblage of data carriers, having: a computer memory for pass-through of a first strip of the collection; the assemblage has at least a first storage medium to which at least a first sub-portion of the first strip is written from computer memory; and once the portion of the collection has been so migrated according to a predetermined structure, a remaining portion of the collection can be written to the source data carrier (to include the source data carrier in the assemblage), the remaining portion being ordered (crunched) in conformity with the predetermined structure.

Abstract: An apparatus comprising a transmit portion and a receive portion. The transmit portion may be configured to present (i) one or more data signals and (ii) a configuration signal, in response to one or more input signals. The receive portion may be configured to receive (i) all of the one or more data signals when operating in a first mode and (ii) less than all of the data signals when operating in a second mode. The first and second modes may be configured in response to the configuration signal.

Abstract: A serial data communication receiver includes a serial data input, first and second equalizers, first and second capture latch circuits, and an equalization control circuit. The first and second equalizers are coupled to the serial data input and have first and second equalized serial data outputs, respectively. Each equalizer has a frequency response that is variable over a range of frequency response settings. The first and second capture latch circuits are coupled to the first and second equalized serial data outputs, respectively, in a phase-locked loop and have first and second recovered data outputs, respectively. The equalization control circuit measures a data eye size of the second equalized serial data output over the range of frequency response settings of the second equalizer and sets the frequency response of the first equalizer to one of the frequency response settings based on the measured data eye sizes.

Abstract: A circuit and associated methods of operation for a standardized scatter/gather list processor component within DMACs and intelligent IOPs. The standardized circuit architecture and methods provide a register interface and associated processing capabilities to simplify firmware processing to save and restore context information regarding block transfer operations that are paused and resumed prior to completion. Furthermore, the invention provides for architecture and associated methods for processing of standard scatter/gather list elements by a standardized scatter/gather list processor embedded within DMACs and IOPs. Specifically, as applied in the context of SCSI or Fiber Channel IOPs, the scatter/gather list processor of the present invention simplifies IOP firmware processing to save the current block transfer context on occurrence of a SCSI disconnect and to restore the saved context on occurrence of a SCSI reselect.

Abstract: A method of forming a semiconductor on insulator structure in a monolithic semiconducting substrate with a bulk semiconductor structure. A first portion of a surface of the monolithic semiconducting substrate is recessed without effecting a second portion of the surface of the monolithic semiconducting substrate. An insulator precursor species is implanted beneath the surface of the recessed first portion of the monolithic semiconducting substrate, and a trench is etched around the implanted and recessed first portion of the monolithic semiconducting substrate. The insulator precursor species is activated to form an insulator layer beneath the surface of the recessed first portion of the monolithic semiconducting substrate. The semiconductor on insulator structure is formed in the first portion of the monolithic semiconducting substrate, and the bulk semiconductor structure is formed in the second portion of the monolithic semiconducting substrate.

Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method involves providing a substrate having an insulating layer with an opening therein configured to receive an inlaid conducting structure. A copper seed layer is formed on the insulating layer and in the opening. The seed layer is implanted with barrier material ions to form an implanted seed layer. Upon the implanted seed layer is formed a bulk copper-containing layer. The substrate is then annealed so that barrier material ions migrate through the seed layer to an interface between the seed layer and the insulating layer to form a final barrier layer. The barrier material can include palladium, chromium, tantalum, magnesium, and molybdenum.

Abstract: A circuit combines the outputs of two or more phase locked loops to reduce jitter to a level below that of an individual phase locked loop. A digital version of the circuit uses a majority function to determine the median value of the phase locked loops. An analog version of the circuit averages the outputs of the phase locked loops.

Abstract: A circuit that may be used with a split transaction bus. The circuit generally comprises a register logic and a compare logic. The register logic may be configured to (i) present a first identification signal associated with a first slave device to perform a first transaction and (ii) store a second identification signal associated with a second slave device in place of the first identification signal responsive to a ready signal presented by the second slave device. The compare logic may be configured to (i) compare the second identification signal with the first identification signal and (ii) present a back off signal responsive to the compare.

Abstract: A DVD player or computer with a DVD drive simultaneously presents multiple angles of video on a display. DVD standards provide for formatting and storing video that was filmed from more than one angle. Desired angles are selected, and the DVD player multiplexes between each angle of the playback to decode video frames for each selected angle. The frames for each angle being played back are filtered down to a size that fits into a fragment of the display. Each of the filtered frames are assembled into a single frame that can be presented on the display to simultaneously playback each angle.

Abstract: An XOR circuit includes XOR function logic. One advantage of the XOR circuit is that the complements of A and B are not required. The XOR circuit receives an enable signal that disables all the load transistors to eliminate static power dissipation of the XOR circuit and always force the output high when disabled. The output signal of the XOR function logic does not swing rail-to-rail and also has a relatively low drive level. To overcome that, cascade transistor stages are used that have small increments in device sizes, preferably widths, between stages. This allows the fastest rise/fall times at the output of the XOR function logic.

Abstract: Provided is a process for forming a semiconductor device having salicided contacts. A concentration of metal is formed at the substrate surface by exposing the substrate to a metal plasma. The concentration of metal is then annealed to produce a salicided contact. In a separate embodiment, the metallization plasma and salicide anneal occur in-situ in one process step.

Abstract: A method of testing the processing of a wafer on a CMP apparatus includes processing a control wafer with the CMP apparatus with a predetermined control consumable combination under a predetermined set of control conditions and generating a control data set which describes the processing of the control wafer with the CMP apparatus, the control data set being based upon the control conditions and a removable rate of the control wafer. The method further includes processing a test wafer with a CMP apparatus with a test consumable combination substantially the same as the control consumable combination under a set of test conditions substantially the same as the set of control conditions. The method further includes generating a test data set which describes the processing of the test wafer with the CMP apparatus.

Abstract: A method for reducing circuit gate count is disclosed. The method generally comprises the steps of (A) generating a new file from a source file and a parameter file, wherein the source file comprises a first circuit defined in a hardware description language, the new file comprises a second circuit defined in the hardware description language, the parameter file comprises a second clock frequency for the second circuit that is faster than a first clock frequency for the first circuit, and the first circuit is functionally equivalent to the second circuit, (B) generating a first gate count by synthesizing a first design from the source file, (C) generating a second gate count by synthesizing a second design from the new file and (D) generating a statistic by comparing the first gate count to the second gate count.

Abstract: A method is presented for self-test and self-repair of a semiconductor memory device. A single built-in self-test (BIST) engine with an extended address range is used to test the entirety of memory (i.e., both redundant and accessible memory portions) as a single array, preferably using a checkerboard bit pattern. An embodiment of the method comprises two stages. In the first stage, faulty rows in each memory portion are identified and their addresses recorded. Known-bad rows in accessible memory are then replaced by known-good redundant rows, and the resulting repaired memory is retested in a second stage. During the second stage, repair of the accessible memory portion is verified, while defects among the redundant portion are ignored. Compared to existing methods, the new method is believed to simplify the interface between the BIST and the built-in self-repair (BISR) circuitry, reduce the overall size of test and repair circuitry, and provide improved test coverage.

Abstract: The present invention is directed to a system and method employing a static logical identifier. In an aspect of the present invention, an input/output interface suitable for communicatively coupling a host with a target device may include at least one port communicatively coupling the input/output interface with a host and at least one port communicatively coupling the input/output interface with a target. A controller is communicatively coupled to the ports. When the controller receives an identifier from the host, the controller generates a logical identifier from the identifier, the logical identifier suitable for being utilized in conjunction with a look-up table to provide access to the target.

Abstract: A method and system for determining and recording a minimal ending video buffer verifier fullness at each of a plurality of entry points in a compressed variable bit rate video bit stream.

Abstract: In a computer (e.g. an 80×86-compatible personal computer) in which peripheral devices (e.g. hard drives, floppy drives, CD-ROMs, etc.) are accessed through more than one chain of handlers for the peripheral devices (e.g. via interrupts 13h and 40h), an improved device handler for a peripheral device (e.g. a device that complies with the “El Torito” standard) is inserted in both chains (e.g. by “hooking” both interrupts 13h and 40h), so the device handler cannot be bypassed when an access request directed to the device handler is passed through either chain and so the device handler can direct the access request to the next device handler in the correct chain, when appropriate.

Abstract: Removal of rough edges in punctured or ruptured pores on the walls of an opening, such as a via and/or trench opening, in a layer of porous dielectric material, in an integrated circuit structure, is carried out to permit satisfactory lining of all exposed surfaces of the porous dielectric material with a barrier layer which prevents contact between a copper filler and the porous dielectric material, and facilitates filling of the completely lined punctured/ruptured pore with such copper filler to eliminate void formation. The rough edges of the punctured/ruptured pores are removed by an isotropic etch of the exposed walls of the opening. Preferably, the dielectric material in the porous dielectric material is a low k dielectric material.