Patents Assigned to LSI Logic
  • Cluster tool reporting system
    Patent number: 6724404
    Abstract: A method for determining an up time of a multi-component tool having discrete elements, where the up time determination is based upon different processes that are to be accomplished in the multi-component tool. The discrete elements of the multi-component tool and the different processes to be accomplished in the multi-component tool are identified. Different tool states for the multi-component tool are determined by setting element states for each of the discrete elements of the multi-component tool. A first possible element state indicates that the discrete element is functional, and a second possible element state indicates that the discrete element is nonfunctional. Possible combinations of the element states of the discrete elements are identified as the different tool states of the multi-component tool.
    Type: Grant
    Filed: February 6, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Thomas C. Hann, Jr., Mark D. Meyer, Theodore O. Meyer
  • Forward error correction apparatus and methods
    Patent number: 6725416
    Abstract: Forward error correction apparatus and methods are described. A forward errro correction method includes: (a) computing syndromes values; (b) computing an erasure location polynomial based upon one or more erasure locations; (c) computing modified syndromes based upon the computed erasure location polynomial and the computed syndrome values; (d) computing coefficients of an error location polynomial based upon the computed modified syndromes; (e) computing a composite error location polynomial based upon the computed coefficients of the error location polynomial; (f) computing a Chien polynomial based upon the computed composite error location polynomial; (g) performing a redundant Chien search on the computed composite error location polynomial to obtain error location values; and (h) evaluating the computed Chien polynomial based upon the error location values to obtain error and erasure values.
    Type: Grant
    Filed: February 4, 2003
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Tan C. Dadurian
  • Amplifier and line driver for broadband communications
    Patent number: 6724219
    Abstract: A line driver for coupling a data transceiver to a transmission line having a load impedance via a transformer with a turns ratio of 1:n includes an input port for receiving an input signal voltage from the data transceiver, an output port for supplying an output signal voltage to the transformer, and an amplifier circuit for amplifying the input signal voltage. The amplifier circuit includes a first output stage, a second output stage coupled to the output port, an output resistor coupled to the first output stage, a feedback path from the first output stage to an input of the amplifier circuit, and a line matching network coupled between the first output stage and the second output stage, for compensating variations in the load impedance, so that a synthesized output impedance of the line driver substantially matches an actual load impedance Z of the transmission line.
    Type: Grant
    Filed: June 15, 2001
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Chun-Sup Kim, Ara Bicakci, Cormac S. Conroy, Sang-Soo Lee
  • Method for minimizing clock skew by relocating a clock buffer until clock skew is within a tolerable limit
    Patent number: 6725389
    Abstract: A method of clock buffer placement for minimizing clock skew includes the steps of (a) constructing a trunk delay model for a plurality of clock cells within a partitioning group, (b) placing a clock buffer at an initial location in the trunk delay model, (c) estimating a clock skew and an insertion delay from the trunk delay model, (d) checking whether the clock skew exceeds a clock skew limit, and (e) if the clock skew exceeds the clock skew limit, then selecting a new location for the clock buffer in the trunk delay model.
    Type: Grant
    Filed: December 11, 2000
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Alexander Tetelbaum, Rajiv Kapur
  • DEBUG mode for a data bus
    Patent number: 6725306
    Abstract: A slave device includes a queue that receives commands or data from a master device for execution on a first-in, first-out basis. A status register is responsive to the queue to provide a STATUS_FULL signal when the queue is full of commands and a STATUS_EMPTY signal when the queue is empty. A configuration register provides a DEBUG signal identifying a maintenance status of the slave device. A bus control provides a QUEUE_FULL signal in response to either (1) the STATUS_FULL signal or (2) the DEBUG signal and not the STATUS_EMPTY signal to split further commands or stall the data bus.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Russell B. Stuber, Robert W. Moss, David O. Sluiter
  • Automatic LAN flow control mechanisms
    Patent number: 6724725
    Abstract: A method operates a media access control device. The method includes (a) detecting the assertion of a flow control condition, (b) generating a PAUSE frame in response to the detection of a flow control condition, the PAUSE frame directing a remote device to PAUSE for a first amount of time, (c) causing the media access device to wait for a second amount of time, the second amount of time being less than or equal to the first amount of time, and (d) generating, upon expiration of the second amount of time and the continued assertion of the flow control condition, an additional PAUSE frame directing a remote device to PAUSE for a first amount of time.
    Type: Grant
    Filed: April 11, 2000
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventors: Stephen F. Dreyer, Eric T. West, Donald W. Alderrou
  • Pad conditioning monitor
    Patent number: 6722948
    Abstract: A modification to a chemical mechanical polishing conditioner of a type having a member with a conditioning surface adapted to apply a force to and condition a polishing pad. The conditioner includes at least one sensor disposed within the member, where the at least one sensor is adapted to sense at least one of an amount of the force applied to the polishing pad and a uniformity across the member of the force applied to the polishing pad. In this manner, the force applied by the conditioner to the pad, and the uniformity of the force applied by the conditioner to the pad, can be sensed. These sensed forces can be monitored, reported, and controlled, thus providing a better controlled chemical mechanical polishing process.
    Type: Grant
    Filed: April 25, 2003
    Date of Patent: April 20, 2004
    Assignee: LSI Logic Corporation
    Inventor: Michael J. Berman
  • Method for deriving a word address and byte offset information
    Patent number: 6721869
    Abstract: A method for addressing a particular location of a memory organized as a plurality of words having an odd number (e.g., three) partitions. Upon receiving an address for a particular memory location, address translation circuitry according to the present invention effectively converts the address to a floating point number. The address translation circuitry then divides the received address by three to determine which word of memory—and which byte—is being addressed. In particular, the quotient of the division process provides the word address, while the remainder provides the byte offset. Memory addressed by the present invention may be organized into “words” of varying length. For example, each “word” may be ninety-six bits wide, with partitions of thirty-two bits each. In this embodiment, the remainder of the division process identifies a particular thirty-two bit partition.
    Type: Grant
    Filed: August 15, 2000
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventor: Gurumani Senthil
  • Buffer partitioning for managing multiple data streams
    Patent number: 6721826
    Abstract: The present invention is directed to a buffer partitioning system and a method employing the system to dynamically partition buffer resources among multiple data streams. The buffer partitioning system utilizes context information relating to the streaming data to control the flow of data through the buffer resource. By including a buffer partitioning system, multiple data streams may be more efficiently transferred through buffer resources thus resulting in faster data transfers.
    Type: Grant
    Filed: September 25, 2001
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventor: Timothy E. Hoglund
  • Algorithm for maintaining maximum streaming performance of mirrored disks
    Patent number: 6721845
    Abstract: A reading algorithm for a set of mirrored disks sends groups of reads to one disk, then sends the next group to the other disk. This provides a more optimal use of disks for sequential reads than previous algorithms. An enhanced version uses snooping of the read requests and switches disks immediately for the read if the requests are not sequential, or within a given number of records of sequential. Additionally, the size of the requests can change the number of requests grouped together in the enhanced version.
    Type: Grant
    Filed: September 24, 2001
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: Roger T. Clegg, Craig Charles McCombs
  • Method and apparatus for fibre channel identification and retrieval
    Patent number: 6721320
    Abstract: The invention relates to an improved Fiber Channel data management technique. More specifically, this patent relates to an improved scheme for managing the related data in related frames that form a sequence. This patent also generally relates to the management of multiple, active sequences which are simultaneously in transit on a Fiber Channel. This invention provides a means for efficiently locating the sequence status block associated with an arbitrary Fiber Channel sequence by using the source identifier field, the originator exchange identifier field and/or the sequence identifier fields of a Fiber Channel frame header to construct a hash table lookup search.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: April 13, 2004
    Assignee: LSI Logic Corporation
    Inventors: Timothy E. Hoglund, Louis H. Odenwald, Jr., Elizabeth G. Rodriguez
  • Multi chip module
    Publication number: 20040065951
    Abstract: A multi chip package, which includes a package substrate having a first side and an opposing second side. The first side is for receiving package electrical connections. Integrated circuits are electrically connected and structurally connected by their first sides to the second side of the package substrate. Heat spreaders are disposed adjacent the second side of the integrated circuits, where one each of the heat spreaders is associated with one each of the integrated circuits. A single stiffener having a first side and an opposing second side covers all of the integrated circuits and heat spreaders, where the first side of the stiffener is disposed adjacent the second side of the heat spreaders.
    Type: Application
    Filed: August 11, 2003
    Publication date: April 8, 2004
    Applicant: LSI Logic Corporation
    Inventors: Leah M. Miller, Kishor Desai
  • Compressed video format with partial picture representation
    Publication number: 20040066851
    Abstract: A method for decoding a digital video bit-stream comprising the steps of (A) receiving the digital video bit-stream having (i) a first portion containing image information and (ii) a second portion containing overscan information and (B) extracting the overscan information from the video bit-stream. The overscan information describes a shape of a overscan region absent from the digital video bit-stream.
    Type: Application
    Filed: October 22, 2002
    Publication date: April 8, 2004
    Applicant: LSI LOGIC CORPORATION
    Inventor: Elliot N. Linzer
  • High speed OC-768 configurable link layer chip
    Publication number: 20040068593
    Abstract: An integrated circuit comprising a plurality of link layer controllers. The plurality of link layer controllers may be configured to operate independently in a first mode and cooperatively in a second mode.
    Type: Application
    Filed: October 8, 2002
    Publication date: April 8, 2004
    Applicant: LSI LOGIC CORPORATION
    Inventors: Victor Helenic, Clinton P. Seeman, Danny C. Vogel
  • Substrate impedance measurement
    Patent number: 6717423
    Abstract: A probe structure with a connector connecting the probe structure to a time domain reflectometry tester, where the connector has a signal conductor and a ground conductor. A back side layer is connected to the connector. A probe side layer with contacts is sandwiched with the back side layer in a layered substrate. The probe side layer has a centrally disposed signal contact and surrounding ground contacts. A conductive layer is disposed between the back side layer and the probe side layer. The conductive layer is connected to the ground conductor of the connector and to the ground contacts of the probe side layer contacts. A via extends from the back side layer to the probe side layer. The via is connected to the signal conductor of the connector, and is also connected to the centrally disposed signal contact of the probe side layer contacts. The via does not make connection with the conductive layer.
    Type: Grant
    Filed: October 9, 2002
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Aritharan Thurairajaratnam, Mohan R. Nagar
  • Method and apparatus for isochronous data transfer with retry capability
    Patent number: 6717947
    Abstract: Isochronous data transfers guarantee data packets are received at a particular frequency and within a prespecified jitter-tolerance. Asynchronous data transfers guarantee data integrity by allowing missed or errant packets to be resent as many times as needed until an error-free packet may be reconstructed at the receiver. Isochronous transfers address real-time needs but do not address the data integrity issue. Asynchronous transfers address the data integrity issue but cannot guarantee error-free data packets will be available so as to meet a real-time constraint. The present invention provides method and apparatus enable isochronous data transfers with improved data integrity. Various link layer and transaction layer mechanisms are taught. An embodiment involving the IEEE 1394 bus specification is addressed in detail.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Fataneh F. Ghodrat, Michael R. Stein, David A. Thomas
  • Hardware chain pull
    Patent number: 6718405
    Abstract: A controller generally comprising a DMA engine, a processor, and a circuit. The DMA engine may be configured to copy from a system memory to a local memory. The processor may be configured to process a message written in the local memory. The circuit may operate independently of the processor. The circuit may be configured to (i) monitor writes to the local memory for the message having a first pointer and (ii) program the DMA engine to copy a first buffer identified by the first pointer in response to the first pointer having a non-null value.
    Type: Grant
    Filed: September 20, 2001
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventor: Jeffrey M. Rogers
  • Method and apparatus for detecting presence of residual polishing slurry subsequent to polishing of a semiconductor wafer
    Patent number: 6716364
    Abstract: A method of detecting presence of a polishing slurry on a semiconductor wafer subsequent to polishing of the wafer includes the step of adding a chemical marker to the polishing slurry. The method also includes the step of polishing a first side of the wafer in order to remove material from the wafer. In addition, the method includes the step of applying the polishing slurry to the first side of the wafer during the polishing step. Moreover, the method includes the step of ceasing the polishing step when the wafer has been polished to a predetermined level. Yet further, the method includes the step of directing incident electromagnetic radiation onto the wafer subsequent to the ceasing step. The method also includes the step of detecting a physical characteristic of resultant electromagnetic radiation which is produced in response to the incident electromagnetic radiation being directed onto the wafer.
    Type: Grant
    Filed: December 10, 2001
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Newell E. Chiesl, III, Gregory L. Burns, Theodore C. Moore
  • Low cost voltage controlled crystal oscillator (VCXO)
    Patent number: 6717483
    Abstract: A circuit generally comprising a tank circuit and an inverter circuit. The tank circuit may be configured to generate a first signal having a frequency of oscillation in response to a second signal. The inverter circuit may be configured to (i) generate the second signal in response to inverting the first signal and (ii) adjust a delay in generating the second signal in response to an input signal to change the frequency of oscillation.
    Type: Grant
    Filed: April 1, 2002
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Yoed I. Nehoran, Yuanping Zhao
  • Interrupt handling mechanism in translator from one instruction set to another
    Patent number: 6718539
    Abstract: An apparatus comprising a translator circuit and a cache. The translator circuit may be configured to (i) translate one or more first instruction codes of a first instruction set into second instruction codes of a second instruction set, (ii) present the second instruction codes to a processor, and (iii) allow interrupts to the processor to be handled seamlessly.
    Type: Grant
    Filed: December 22, 2000
    Date of Patent: April 6, 2004
    Assignee: LSI Logic Corporation
    Inventors: Ariel Cohen, Ronen Perets, Boris Zemlyak