Abstract: Methods and associated structure for updating and propagating firmware updates in a multiple redundant controller storage subsystem. The methods of the present invention assure that the storage subsystem remains operable processing host system I/O requests while the redundant controllers manage the firmware update process. At least one controller of a plurality of redundant controllers in the system remains available for processing of host I/O requests as the controllers manage the firmware update process. A management client process operable on an administrative system coupled to the first of the redundant storage controllers transfers a structured firmware file to the first redundant controller. The management client need perform no further management of the update process. Rather, the controller themselves manage the process in accordance with metadata stored within the firmware file along with the programmed instructions to be updated.

Abstract: An apparatus comprising a plurality of flip-flops each comprising (i) a first input, (ii) a second input and (iii) an output, where (a) each of the outputs are coupled to the first input of a subsequent flip-flop to form a chain, (b) the first input of a first of the flip-flops receives a pattern signal, (c) each of the second inputs receives a respective first logic signal, and (d) each of the outputs presents a respective second logic signal in response to the signals received at the first and second inputs, a pattern generator configured to generate the pattern signal, and a checking circuit configured to generate a check signal in response to the second logic signal of a last of the flip-flops. The pattern signal and the first logic signals are generally selected to influence a behavior of the apparatus.

Abstract: An apparatus comprising a plurality of IO queues and a logic circuit. The plurality of IO queues each may be configured to receive a respective IO request and present the IO request in response to a trigger signal. The logic circuit may be configured to (a) (i) receive one or more of the IO requests and (ii) serially coalesce the IO requests in response to a respective device identification (ID) of the IO requests, and (iii) present one or more of the coalesced IO requests as one or more respective context queue requests in response to the trigger signal and (b) generate the trigger signal when a current queue count is equal to a maximum queue depth.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate a random number signal, (ii) read a data signal, and (iii) generate one or more control signals. The second circuit may be configured to (i) store the random number signal, (ii) receive and store a decoded video signal, and (iii) present the data signal. The first circuit may be further configured to compare the data signal with the random number signal and (i) when the data signal matches the random number signal generate a first of the control signals and (ii) when the data signal fails to match the random number signal generate a second of the control signals.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to (i) generate a sorted list of permanent unique identifiers according to predetermined criteria and (ii) associate a logical identification with a physical address identifier using the sorted list. The second circuit may be configured to manage communications between a host and a target. The second circuit may (i) communicate with the host using the logical identification and (ii) communicate with the target using the physical address identifier. The communications between the host and the target may be unaffected by changes in the physical address identifier. The function of the first circuit and/or the second circuit may be implemented, among other examples, in software and/or firmware.

Abstract: A method for insulating a bonding wire that includes the steps of attaching a bonding wire to a bond pad and coating the bonding wire with an insulating liquid while drawing the bonding wire through a bond tool from the bond pad to a package lead.

Abstract: A circuit comprising a cache memory, a memory management unit and a logic circuit. The cache memory may be configured as a plurality of associative sets. The memory management unit may be configured to determine a data tag from an address of a data item. The logic circuit may be configured to (i) determine a selected set from the plurality of associative sets that produces a cache-hit for the data tag, (ii) buffer the address and the data item during a cycle, and (iii) present the data item to the cache memory for storing in the selected set during a subsequent cycle.

Abstract: A system and method for dynamically generating the topology of a storage array network by linking information concerning hosts and clusters along with information about host port adapters. Namely, each host identifies itself to all controllers and provides information in a command that allows the controller to know which host and cluster, if applicable, is associated with the host port adapter through which the command was issued. In addition, the topology is automatically updated anytime there is a change on the network such as a new device was added or a host port adapter was replaced.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or logic cone of cells. A different logic cone is derived for each of the multiple failing output signals at output pads.

Abstract: A method and apparatus are disclosed for asynchronous testing of multiport memories. In one embodiment, the apparatus includes a built-in self-test (BIST) unit coupled to a multiport memory module and configured to apply a pattern of read and write test operations concurrently to multiple ports of the memory. The pattern of test operations may be any standard or customized pattern designed to establish the functionality of the multiport memory. The test operations to different ports are clocked by different clock signals so that the clock signals may be offset relative to each other by an adjustable or preset clock skew. Certain clock skews cause transitions to occur on signal lines in the memory array at the most sensitive portion(s) of a read cycle. The timing of these transitions, in combination with the presence of high-resistivity bridge faults, sufficiently disturbs the read cycle so as to cause a read error, thereby enabling detection of the bridge faults.

Abstract: A data storage system and a method of managing data in the storage system. A method of performing a write to a data storage system, including a first storage device and a second storage device, may include writing a first set of header information to a first storage device and a second storage device. The first set of header information includes a first sequence number and a second sequence number, in which the first set of header information includes a first sequence number incremented to indicate a change from the second sequence number. The method may also include returning status of completion of writing the second set of header information. Invalid data or an interruption may also be detected by examining the first and second sequence numbers. Data is written to the first storage device and the second storage device. Then, a second set of header information is written to a first storage device and a second storage device.

Abstract: An input/output array of an integrated circuit comprises concentric rings of input/output tiles. The peripheral input/output tiles are adjacently arranged along the periphery of the integrated circuit to form a peripheral ring. Each of the peripheral input/output tiles is associated with a corresponding peripheral input/output device group having x1 number of input/output devices. Each peripheral input/output tile includes x1 number of signal contacts for coupling signals to corresponding ones of the x1 number of input/output devices, y1 number of input/output driver voltage contacts for coupling a source voltage to drivers of the x1 number of input/output devices, and z1 number of ground contacts. The interior input/output tiles are adjacently arranged within the interior of the integrated circuit to form n number of substantially concentric interior rings, where n is greater than or equal to one.

Abstract: A first circuit and a second circuit. The first circuit may be configured to generate a first intermediate signal, a second intermediate signal, and a third intermediate signal in response to a first control signal, a second control signal, a third control signal, a reference signal and an output clock signal. The second circuit may be configured to generate an output signal in response to the first intermediate signal, the second intermediate signal, and the third intermediate signal. The output signal may indicate a lock condition between a feedback signal and the reference signal.

Abstract: Structure and associated methods of operation for an enhanced boundary scan register structure in an integrated circuit that permits flexible application of stuck-at faults or normal operation on each I/O pad of the IC. Each pad may be individually controlled to force a desired stuck-at fault or may be permitted to operate normally. The additional structure integrates with existing boundary scan register structures to minimize the need for additional logic and latches as compared to prior techniques and to minimize additional globally routed signals. Additional commands decoded by TAP command processing provides desired specialized control for the enhanced boundary scan register.

Abstract: An apparatus comprising a counter circuit, a first register circuit, a second register circuit and an output circuit. The counter circuit may be configured to generate a count signal in response to a data input signal and a first clock signal operating in a first clock domain. The first register circuit may be configured to generate a first control signal in response to the count signal. The second register circuit may be configured to generate a second control signal in response to the data input signal. The output circuit may be configured to generate a data output signal operating in a second clock domain in response to the first control signal, the second control signal, the count signal, and a second clock signal.

Abstract: A method for analyzing an electrical characteristic of wire segments configured as one or more power meshes in an integrated circuit (IC) core comprising the steps of (A) specifying design information corresponding to the power meshes, (B) specifying at least one type of analysis to be performed, where the analysis comprises (i) generating a file corresponding to the IC core in a format compatible with an electronic circuit simulator and (ii) calculating the electrical characteristic of the wire segments via the circuit simulator, and (C) displaying the calculated electrical characteristic.

Abstract: A method and apparatus are provided for calibrating first and second digital-to-analog converters (DACs). The apparatus has a normal input and a test input. A first correction circuit selectively modifies either the normal input or the test input by a first gain correction value and a first offset correction value to produce a first corrected value. A second correction circuit selectively modifies either the normal input or the test input by a second gain correction value and a second offset correction value to produce a second corrected value. A first DAC operates on the first corrected output and has a first analog output. A second DAC operates on the second corrected output and has a second analog output. A calibration control circuit has first and second inputs coupled to the first and second analog outputs, respectively, and generates the first and second gain correction values and the first and second offset correction values as a function of the first and second analog outputs.

Abstract: A method of translating a register transfer level code model includes receiving as inputs a user defined primitives map file, a truth table map file, a gate primitives map file, a register transfer level description file of a library cell, a standard delay format file, and a pin order information file for the register transfer level code model; creating data structures for a VITAL model; parsing at least one of the user defined primitives map file, the truth table map file, the gate primitives map file, the register transfer level description file, and the standard delay format file to generate an equivalent VITAL model in the data structures created for the VITAL model wherein the VITAL model is functionally equivalent to the register transfer level code model; and generating as output a VITAL model file from the data structures created for the VITAL model.

Abstract: A heterogeneous integrated circuit having a digital signal processor and at least one programmable logic core. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers.

Abstract: A semiconductor memory device includes at least one memory cell for storing digital data. A local sense amplifier is operably coupled to the at least one memory cell for receiving a first signal representative of the digital data stored in the at least one memory cell, and outputting a second signal representative of the received first signal in response to a first strobe signal. A global sense amplifier is operably coupled to the local sense amplifier for receiving the second signal, and outputting a third signal representative of the received second signal in response to a second strobe signal. Dummy circuitry is provided for-enabling generation of the first and second strobe signals.