Abstract: A method for determining an effective fatal defect count based on defects in a plurality of inspected integrated circuits includes acquiring defect information related to defects in the integrated circuits, and assigning defect weight values to each of the defects based on the defect information. The defect weight values are in N number of defect weight value ranges, including a lowest and a highest defect weight value range. For each integrated circuit, a heaviest defect is determined, where the heaviest defect is the defect on each integrated circuit having a highest defect weight value. For each of the N number of defect weight value ranges, a total number T(n) of the heaviest defects having a defect weight value within a defect weight value range n is determined, where n equals one to N.

Abstract: A method for generating one or more hardmacro technology files comprising the steps of determining a netlist, generating a timing constraints file in response to (i) the netlist and (ii) a time budget, and generating the hardmacro technology files in response to (i) the netlist and (ii) the timing constraints file.

Abstract: A method of transferring a block of graphics data for display on a screen along a data bus between a processing block and a plurality of addresses in memory comprising the steps of (A) generating a first and a second X and Y coordinate value for each of one or more portions of data to be transferred, (B) calculating a respective address in memory of the plurality of addresses corresponding to each of the first and second coordinate values, (C) accessing the addresses to effect the data transfer, (D) determining if a plurality of bus criteria are met and (E) enabling or inhibiting transfer of the block of data in a data burst in response to the plurality of criterias being met.

Abstract: A software program to translate a Verilog UDP (User Defined Primitive) into basic logic gates, in order to allow easier porting into other HDL languages and non-Verilog models, such as the LogicVision model. In a preferred embodiment the program is in Perl script, and reads in a Verilog source file. On finding a UDP, the script writes out a gate level description of the UDP into a Perl hash data structure, which is later used to output a LogicVision model.

Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

Abstract: A power distribution system for distributing external power across a die is disclosed, wherein the die has horizontal and vertical centerlines. The system and method include providing a power mesh that includes a plurality of V-shaped trunks patterned as concentric diagonal trunks extending from the horizontal and vertical centerlines of the die towards the periphery of the die.

Abstract: A method of circuit design for designing integrated circuits with one or more embedded memories. A placement is generated for timing critical logic associated with each included embedded memory in a logic design. An augmented memory boundary is generated for said each included memory. Each augmented memory boundary encompasses one embedded memory and associated said timing critical logic.

Abstract: An intensity filter for deep UV lithography enhances contrast and also therefore increases the resolution of patterned images by passing only intensities that fall within a specific minimum threshold value, resulting in a more exact aerial image replicating the mask image. This device is a different approach to contrast enhancement that is distinguished from previous methods by eliminating the need for an extra layer of contrast enhancement on top of the resist, thereby reducing the number of processing steps in semiconductor fabrication.

Abstract: An apparatus comprising a memory, a plurality of modules, an address translation unit and a controller. The memory may be arranged as a plurality of memory banks. Each of the plurality of modules may be configured to generate one or more addresses for accessing a particular one of the plurality of memory banks. The address translation unit may be configured to modify the one or more addresses in response to a control signal. The controller may be configured to generate the control signal in response to a computer executable instruction.

Abstract: A method for inserting and reading probe points in a silicon embedded testbench comprising the steps of (a) reading a simulation list of probe points, (b) enabling access to the list of probe points, (c) generating a core, and (d) displaying or comparing the probe points.

Abstract: The present invention provides a comprehensive design environment defining a system architecture and methodology that may integrate interconnects, cores, ePLC, re-configurable processors and software into a manageable and predictable system designs that achieve on-time system IC design results meeting desired specifications and budgets. For example, an interscalable interconnect maybe provided that is scalable and isochronous capable. Additionally, an abstract language may be provided to be able to describe interconnecting core functions. Further, a self-programmable chip may be provided that, upon receiving a construct, it could program itself to achieve the desired functionality, such as through the use of on-chip knowledge and the like.

Abstract: An apparatus comprising a first circuit and a logic circuit. The first circuit may be configured to generate a first output signal in response to (i) an input signal, (ii) a first control signal and (iii) a second control signal. The logic circuit may be configured to generate (i) a second output signal, (ii) the first control signal and (iii) the second control signal in response to a predetermined portion of the input signal.

Abstract: An integrated circuit having an electrically insulating layer of an electrically nonconductive material, where the electrically insulating layer is disposed between at least two electrically conductive elements. The electrically nonconductive material is selected from a group of materials having a k value that decreases when subjected to thermal treatment. The electrically nonconductive material is most preferably a boro siloxane.

Abstract: The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in the power distribution grid are generally L-shaped. Thus, the electrical conductors are arranged generally in symmetrical quadrants within which the electrical conductors extend from one side edge of the IC chip to a generally right-angled corner and then to a second side edge that is adjacent to the first side edge.

Abstract: A clock tree uses a temporary clock buffer or reference signal in a clock tree deskew circuit to dynamically minimize skew in a variable delay clock signal that synchronizes operation of synchronized circuit components of an integrated circuit. Skew between the temporary clock buffer signals are minimized by providing identical path lengths and path geometries. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. When the tree deskew circuit is deskewed for a multilevel clock tree, the temporary clock net of that level of the clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock tree deskew circuit adjusts the variable delay clock buffer signal of each pair toward the temporary clock buffer signal of the pair to reduce the skew between the two clock buffer signals.

Abstract: A heterogeneous integrated circuit having a digital signal processor and two programmable logic cores, PLCs. An AMBA AHB couples the cores and most other functional units on the IC. The PLCs are also coupled to the DSP through a separate DMA sharing unit to the DSP, and particularly to the DSP memory. The memory sharing arrangement provides a separate high-speed data transfer mechanism between the PLCs and the DSP. The AMBA AHB allows the DSP to control the PLC operations without interference with high-speed data transfers. The DSP may reconfigure one PLC using the AMBA AHB, while it is processing data with the other PLC.

Abstract: A heat spreader for use with an integrated circuit in a package, where the heat spreader is formed as a plate having a centrally disposed aperture with a diameter that is smaller than a minimum diameter of the integrated circuit. The heat spreader has an overall diameter that is no greater than a minimum diameter of the package. In this manner, the aperture in the heat spreader allows the plastic injected through a top gated mold form to pass through the heat spreader and more uniformly encapsulate the integrated circuit.

Abstract: Data transfers from the peripheral interface of a disk array to a data buffer are snooped to determine if the starting address of a data transfer matches an entry in a list of starting addresses for requested data. If a match is identified, third party transfer is initiated and the data is simultaneously transferred to the host interface of the host system. The resulting data bandwidth is increased. A throttling/suspension mechanism can temporarily or indefinitely hold up actual data movement into the data buffer to allow for temporary buffering and interface speed matching as data is transferred to the host interface.

Abstract: An active heat sink uses a liquid coolant to transfer heat from a hot zone to a cool zone. The liquid coolant is propelled using a motor comprised of a plurality of external coils that are in magnetic communication with a plurality of magnets attached to a pump gear. The motor does not require any penetration of the liquid cavity. Further, the heat pump may have a temperature monitoring circuit to determine whether or not the pump should be activated.

Abstract: A power-on reset circuit is provided, which includes a ground input, a power input having a voltage relative to the ground input, a reset output, a self-initializing latch, a high voltage trigger circuit and a discharge circuit. The self-initializing latch has first and second latch nodes which are initialized to logic high and low states, respectively, upon initial application of power to the power input. One of the first and second latch nodes is coupled to the reset output. The high voltage trigger circuit is coupled to the first latch node and reverses the states of the first and second latch nodes when the voltage rises above a high trigger voltage. The discharge circuit is coupled to the second latch node and has a switch circuit, which selectively couples the second latch node to the ground input when the voltage falls below a low trigger voltage.