Abstract: The present invention provides a method of forming a semiconductor device fuse and a semiconductor device fuse structure. A first dielectric layer is formed on top of a metal layer in a semiconductor device. The dielectric layer is patterned to provide access to at least two contacts in the metal layer. A conductive metal layer is deposited and patterned to form a fuse between the fuse contacts. A second dielectric layer is deposited on the conductive metal layer.

Abstract: A slew based clock multiplier which outputs a fraction of a master clock without having to use, as a reference, an edge of a higher frequency clock, and without having to use precision delay cells to delay edges of the master clock. The slew based clock multiplier can be configured to provide such an output as the result of a ratio of input current sources, a ratio of capacitors in the circuit, or as a result of a combination of the two.

Abstract: An apparatus comprising a first tool configured to generate one or more parameter signals in response to (i) one or more control signals and (ii) an input signal and a second tool configured to generate one or more edited bitstreams in response to (i) one or more bitstreams and (ii) the one or more parameter signals.

Abstract: The present invention is directed to a simple and scalable RAID XOR assist logic with overlapped operations. An apparatus suitable for performing overlapped operations may include an exclusive OR (XOR) unit suitable for performing an exclusive OR (XOR) operation. A memory communicatively coupled to the XOR unit, wherein the memory is suitable for storing a first item of data and a second item of data thereby enabling overlapped operations of the exclusive OR (XOR) unit.

Abstract: A signal amplitude comparator which includes a first input that receives an input signal and generates an output signal that is a non-linear function of the input signal, and a second input circuit that receives a reference input signal and generates a second output signal that generally tracks process, temperature and supply variation. The signal amplitude comparator also includes an amplifier, a filter and a comparator. The amplifier amplifies a signal difference between the first and second output signals and outputs a train of pulses if a peak of the input signal exceeds the reference input signal. A second reference signal is applied to the comparator which generates an output which indicates whether the input signal exceeds a pre-determined threshold value. The signal amplitude comparator also includes a pair of input amplifiers which receive and translate the input and reference input signals to levels suitable for the input circuits.

Abstract: The present invention is directed to a spanning tree method for K dimensional space. To address timing driven buffer insertion and clock routing problems clusters of points must be constructed in 3-dimensional space. The first and second dimensions are coordinates on a plane, while the third dimension is time which is arrival pin time for buffers insertion and clock latency for clock routing. In a first aspect of the present invention, a method includes partitioning an input set of points into a binary tree of partitions so that each leaf partition has maximally a defined number of points. Graph edges are made for the points by connecting each point to its closest points in every of 2K subspaces and the number of graph nodes is then reduced to a predefined value.

Abstract: A method for testing integrated circuits is provided. The method includes providing an excitation voltage to a device, such as a MOSFET. A power supply voltage is also provided to the device, such as a drain to source voltage or VCC. The quiescent power supply current of the device is then measured, such as the IDDQ of the MOSFET. The power supply voltage to the device is then varied, and it is determined whether a change in the IDDQ of the device exceeds a predetermined allowable change.

Abstract: An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an analog-to-digital converter, a Hilbert transform filter, a sideband selection switch, a complex multiplier, a carrier recovery. loop, a matched filter, and a decimator. The analog-to-digital converter oversamples an intermediate frequency (IF) signal from the tuner, and the Hilbert transform filter generates a Hilbert transform of the digital IF signal. An analytic IF signal can be generated from the digital IF signal by multiplying the Hilbert transform of the digital IF signal by j(=sqrt(−1)), and adding the resulting imaginary-valued signal to the digital IF signal. The sideband selection switch can “flip” the analytic IF signal by inverting the imaginary-valued signal.

Abstract: The present invention is directed to a system and method of retaining peripheral ordering. A method for retaining peripheral ordering in an information handling system may include reading an ordered peripheral list (OPL) from a nonvolatile memory. A list of active peripherals attached to an I/O interface controller is obtained. An order of peripherals from the ordered peripheral list (OPL) is identified and assignments are assigned to the active peripherals attached to the I/O interface controller corresponding to the ordered peripheral list (OPL).

Abstract: A method for depositing a metal conduction layer in a feature of a substrate is provided. The method includes forming the feature in the substrate, the feature having a width dimension of less than about a tenth of a micron. A barrier layer is deposited on the substrate, preferably using a self ionized plasma deposition process, where the barrier layer has a thickness of no more than about three hundred angstroms. A substantially continuous seed layer is deposited on the barrier layer, where the seed layer has a thickness of less than about three hundred angstroms. A conduction layer is deposited on the seed layer from an alkaline electroplating bath, where the electroplating bath contains an electroplating solution selected from the group consisting a pyrophosphate solution, an alkaline cyanide solution and an alkaline metal ion complexing solution. The process is adaptable to electroplating features on a substrate wherein the features have a width dimension of less than about one tenth of a micron.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to transfer data between a plurality of first ports and a second port via a single port memory in response to one or more control signals. The second circuit may be configured to generate the one or more control signals, wherein the memory is time shared among the second port and the plurality of first ports.

Abstract: A method for retroactively recording from a circular buffer comprising the steps of (A) determining a starting point in the circular buffer, (B) generating a linear buffer by breaking the circular buffer before the starting point and (C) appending to an ending point of the linear buffer.

Abstract: An apparatus comprising a plurality of serially coupled delay cells configured to generate an output signal having a frequency varied in response to a control signal. Each of the delay cells may be configured to generate one or more intermediate signals in response to the control signal and present the intermediate signals to a next of the delay cells. One or more next to the last of the intermediate signals may be fed back to a first of the delay cells. One or more last of the intermediate signals may be presented as the output signal.

Abstract: A method for verifying a path coverage of a circuit design. The method generally comprises the steps of implementing a hardware description language to include a plurality of monitors for a plurality of nodes of the circuit design, monitoring the nodes of a programmable circuit implementing the circuit design in real-time to capture node data, and assessing the node data to determine the path coverage.

Abstract: An apparatus having a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.

Abstract: A memory manager for managing allocation of addresses in the memory is structured as a hierarchical tree having a top vertex, a bottom level and at least one intermediate level. The bottom level contains a plurality of bottom vertices each containing a plurality of representations of a Free or Taken status of respective addresses in the memory. Each intermediate contains at least one hierarchy vertex containing a plurality of labels such that each label is associated with a child vertex and defines whether or not a path that includes the respective child vertex ends in a respective bottom level vertex containing at least one Free representation. An allocation command changes the representation of the first Free address to Taken and a free command changes the representation of a specified address to Free. The labels in hierarchical vertices are changed to reflect the path conditions to the bottom vertices.

Abstract: A method of repeater insertion in a hierarchical integrated circuit includes defining an initial floorplan for a parent macro at a parent level in a hierarchical circuit design; passing outline and pin locations from the parent macro to a child macro sharing a common area with the parent macro; defining or modifying a floor plan for the child macro at a child level in the hierarchical circuit design in response to the outline and pin locations passed from the parent macro; passing physical restrictions in the child macro from the child macro to the parent macro; determining a location for a cell at the parent level of the hierarchical circuit design in an area of the parent macro shared by the child macro in response to the physical restrictions passed from the child macro; passing physical constraints in the parent macro associated with placement and routing of the cell from the parent level to the child macro; and generating an abstract representation for the child macro at the child level that includes an

Abstract: An apparatus comprising a plurality of serially cascaded delay cells each configured to generate a phase of a multi-phase signal and an intermediate signal, where (i) each of the delay cells is generally configured to respond to a bias signal and one of the intermediate signals and (ii) a first of the delay cells is generally configured to respond to an input signal.

Abstract: A method for developing a circuit is disclosed. The method generally comprises the steps of (A) generating a solution space having a dimension for each of a plurality of parameters for the circuit, (B) evaluating a plurality of instances of the circuit in the solution space through a software simulation, (C) evaluating the instances through a hardware simulation, and (D) updating the instances in response to the software simulation and the hardware simulation to approach an optimum instance of the instances for the circuit.

Abstract: An apparatus comprising a first circuit, a second circuit, and a third circuit. The first circuit may be configured to generate a first phase control signal in response to a phase difference between an input clock signal and an output clock signal. The second circuit may be configured to generate a second phase control signal in response to a phase adjust signal. The third circuit may be configured to generate the output clock signal in response to a phase adjustment of the input clock signal. The phase adjustment may be generated in response to a sum of the first and second phase control signals.