Abstract: An apparatus having a first circuit and a second circuit is disclosed. The first circuit may be configured to generate statistics of a region of a memory circuit as part of a read scrub of the region. The region may have multiple units of data. The memory circuit may be configured to store the data in a nonvolatile condition. The second circuit is generally configured to (i) track one or more parameters of the region based on the statistics, (ii) determine when one or more of the statistics of one or more outliers of the units in the region exceeds a corresponding threshold and (iii) track the parameters of the outlier units separately from the parameters of the region in response to exceeding the corresponding threshold. The parameters generally control one or more reference voltages used to read the data from the region.

Abstract: Disclosed is a method and system for deep packet buffering on a switch core comprising an ingress and egress deep packet buffer and an external deep packet buffer.

Abstract: A method for back-off retry with priority routing includes routing a data transfer between an input of a single, cohesive SAS expander and an output of the SAS expander via at least one inter-expander link (IEL), the expander including a first SAS expander and at least one additional SAS expander. The method includes routing a first OPEN request on a direct path through the first SAS expander to a port of a device and routing a second OPEN request on an alternate path from the first SAS expander and through a second SAS expander to the port of the device. The method further includes, upon determination of a failed link or a busy link, re-routing the data transfer from the second SAS expander to the first SAS expander or a third SAS expander, or retrying the data transfer through the second SAS expander.

Abstract: The disclosure is directed to detection of a sync mark location for at least one data sector of a disk by processing a first sector and at least a second sector in parallel. A first set of data samples from the first sector is reframed according to one or more sync mark locations based upon a first selected sync mark location, and a second set of data samples from the second sector is reframed according to one or more sync mark locations based upon a second selected sync mark location. The first set of data samples and the second set of data samples are iteratively reframed and decoded until the first sector or the second sector converges or until all possible sync mark locations have been attempted.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, and a reliability monitor circuit. The data detector circuit is operable to apply a data detection algorithm to a data set to yield a detected output that includes soft data. The reliability monitor circuit is operable to determine a proxy error count based at least in part on the soft data, and to modify a parameter governing an operation of the data processing system based at least in part on the proxy error count.

Abstract: An apparatus comprises read channel circuitry and signal processing circuitry associated with the read channel circuitry. The signal processing circuitry is configured to: equalize a digital data signal; align the equalized digital data signal; determine a detector reliability metric based at least in part on the aligned equalized digital data signal; perform an iterative decoding process to determine a decoded digital data signal using the detector reliability metric; adjust the aligned equalized digital data signal using the decoded digital data signal; and repeat at least determining the detector reliability metric and performing the iterative decoding process using the adjusted equalized digital data signal.

Abstract: A communication port and method of adapting a transmit filter in the port to reduce receive errors by a receiver coupled to the transmit filter via a communication channel. The filter has coefficients that are adjusted in response to a first adaptation gain value, decision bits, and receiver error values. During a first time period, the coefficients are adjusted until changes in the coefficients are less than a first threshold amount. Then during a second time period, the coefficients are adjusted using a second adaptation gain value until changes in the coefficients are less than a second threshold amount. The second adaptation gain value is less than the first adaptation gain value and the second threshold amount being less than the first threshold amount. By using two or more adjustment periods with different gain values, the filter is adapted faster than using a single adjustment period with fixed adaptation gain.

Abstract: In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.

Abstract: A method of printing an image on a wafer. The method includes the steps of printing a main image, wherein the main image includes fields which are fully on the wafer, and printing an alternate image, wherein the alternate image includes fields which are only partially on the wafer. The alternate image could be placed on a separate mask which is loaded onto the exposure tool after the mask with the main image has completed printing. Alternatively, it could be an extra image specially inserted on the mask with the main image for that layer.

Abstract: In one embodiment of a header-compression method, a 32-bit timestamp value is divided by a 16- or 8-bit stride value using a plurality of 16/8-bit division operations, each performed using a corresponding hardware instruction issued to an arithmetic logic unit (ALU) of the corresponding communication device, such as an access terminal or a base station of a communication system. When specialized 32/16-bit and/or 32/8-bit division-logic circuitry is not available in the ALU, embodiments of the header-compression method can advantageously be used to improve the speed and efficiency of timestamp compression in communication devices.

Abstract: A method for determining floating tap positions in a DFE of a receiver is disclosed. The method include providing a group of floating taps for the DFE; obtaining a baseline eye opening value for the receiver when the group of floating taps is disabled; providing a plurality of floating tap distribution configurations, each specifying a distribution configuration for the group of floating taps within the DFE; obtaining a plurality of eye opening values for the receiver, each particular eye opening value corresponding to a particular floating tap distribution configuration when the group of floating taps are distributed within the DFE according to the particular floating tap distribution configuration; comparing each of the plurality of eye opening values against the baseline eye opening value; and identifying an optimal floating tap distribution configuration based on the comparison of each of the plurality of eye opening values against the baseline eye opening value.

Abstract: The present invention is related to systems and methods for applying a data decode algorithm to different rotations or modifications of a decoder input as part of data processing.

Abstract: Various embodiments of the present invention provide systems and methods for monitoring out of order data decoding. For example, a method for monitoring out of order data processing is provided that includes receiving a plurality of data sets that is associated with a plurality of identifiers with each of the plurality of identifiers indicates a respective one of the plurality of data sets; storing each of the plurality of identifiers in a FIFO memory in an order that the corresponding data sets of the plurality of data sets was received; processing the plurality of data sets such that at least one of the plurality of data sets is provided as an output data set; accessing the next available identifier from the FIFO memory; and asserting an out of order signal when the next available identifier is not the same as the identifier associated with the output data set.

Abstract: An apparatus of modular trip mechanism and auxiliary mechanism for a circuit breaker comprises an auxiliary mechanism module including a first micro switch to output an electrical signal indicating an ON/OFF position of the circuit breaker, a first shaft contact lever mechanism to operate the first micro switch by contacting the switching shaft or receiving an artificial pressing force, a second micro switch to output an electrical signal indicating whether a trip operation of the circuit breaker has been performed, and a second lever to operate the second micro switch by contacting the switching shaft or receiving an artificial pressing force; and a trip mechanism module including an electromagnetic trip device to operate a trip bar to trigger the circuit breaker to a trip position in response to a trip control signal from an overcurrent relay or a test trip control signal from a test signal generating source.

Abstract: Methods and systems for data reconstruction following drive failures may include: storing data across two or more drives in one or more data stripes, each data stripe including two or more drive extents; detecting a degradation of a drive containing a drive extent associated with a first data stripe; assigning a reconstruction priority to the drive extent associated with the first data stripe; detecting a degradation of a drive containing a drive extent associated with a second data stripe; and assigning a reconstruction priority to the drive extent associated with the second data stripe.

Abstract: Interface circuitry of a storage device or other type of processing device comprises at least one data path, and an adaptive power supply configured to provide a variable supply voltage to the data path. The adaptive power supply comprises a reference voltage circuit having a plurality of field effect transistors collectively configured to provide a variable reference voltage, with different ones of the field effect transistors being biased into different operating regions. For example, a first subset of the field effect transistors may each be biased into a linear region such that the variable reference voltage tracks variations in on-resistance of one or more corresponding field effect transistors of the data path, and a second subset of the field effect transistors may each be biased into a saturation region such that the variable reference voltage tracks variations in threshold voltage of the corresponding field effect transistors of the data path.

Abstract: A method of designing an integrated circuit, an EDA tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method includes: (1) generating a set of constraint equations representing clock-insertion delay values for the integrated circuit as variables, (2) determining bounds on each of the clock-insertion delay values based on the constraint equations and (3) generating a set of closing commands based on the bounds for driving a design of the integrated circuit to closure, wherein each step of the method is carried out by at least one EDA tool.

Abstract: An optical disk playback device comprises one or more lasers, an optical assembly, an optical detector, and controller circuitry coupled to the optical detector. The optical assembly is configured to direct incident light from the one or more lasers so as to form first and second scanning spots on a surface of an optical disk, and is further configured to direct corresponding reflected light from the first and second scanning spots on the surface of the optical disk to the optical detector. The optical detector is configured to process the reflected light from the first and second scanning spots to generate respective first and second data streams, and the controller circuitry is configured to generate a three-dimensional image signal from the first and second data streams.

Abstract: Software Digital Front End (SoftDFE) signal processing techniques are provided. One or more digital front end (DFE) functions are performed on a signal in software by executing one or more specialized instructions on a processor to perform the one or more digital front end (DFE) functions on the signal, wherein the processor has an instruction set comprised of one or more of linear and non-linear instructions. A block of samples comprised of a plurality of data samples is optionally formed and the digital front end (DFE) functions are performed on the block of samples. The specialized instructions can include a vector convolution function, a complex exponential function, an xk function, a vector compare instruction, a vector max( ) instruction, a vector multiplication instruction, a vector addition instruction, a vector sqrt( ) instruction, a vector 1/x instruction, and a user-defined non-linear instruction.

Abstract: A method for managing redundancy of data in a solid-state cache system including at least three solid-state storage modules. The method may include designating one or more extents of each dirty mirror pair to be of a particular priority order of at least two priority orders. The at least two priority orders can include at least a highest priority order. The highest priority order can have a higher relative priority than the other priority orders. The method may also include performing at least one redundancy conversion iteration. Each redundancy conversion iteration includes converting extents of at least two dirty mirror pairs into at least one RAID 5 group and at least one unconverted extent. The extents of the at least two dirty mirror pairs can include extents designated to be of a highest remaining priority order. Each redundancy conversion iteration can also include deallocating the at least one unconverted extent.