Abstract: A method for fabricating a solar cell module comprises: dispersing carbon nanotubes into a soldering flux; spraying the soldering flux including the carbon nanotubes, onto connection parts between solar cell devices and an interconnector; and connecting the solar cell devices with the interconnector using the soldering flux.

Abstract: A method for broadcast forwarding in a SAS topology having a zoned portion of a service delivery system (ZPSDS) is disclosed. The ZPSDS includes at least a first zoning expander and a second zoning expander. The method includes originating a broadcast primitive on the first zoning expander; forwarding solely the broadcast primitive to the second zoning expander from the first zoning expander; initiating a discovery process from the second zoning expander upon receiving the broadcast primitive; and generating a source zone group list upon completion of the discovery process.

Abstract: Described embodiments provide a method of transferring data from host devices to a media controller. The media controller generates a transfer context for each write request received from a host device. Receive-data threads corresponding to data transfer contexts for each transfer context are generated, each receive-data thread corresponding to a data transfer between a host device and the media controller. Buffer threads corresponding to data transfer contexts for each transfer context are generated, each buffer thread corresponding to a data transfer between the receive data path and a buffer subsystem. The receive-data and buffer threads are tracked for each transfer context. For each tracked transfer context, data from the receive datapath is iteratively transferred to the buffer subsystem for a previous data transfer context of the buffer thread while data from the host device is transferred to the receive datapath for a subsequent data transfer context of the receive-data thread.

Abstract: A system and method for optimizing slave transaction ID width based on sparse connection between multiple masters and multiple slaves in a multilayer multilevel interconnect system-on-chip (SOC) architecture are disclosed. In one embodiment, slave transaction ID widths are computed for a first processing subsystem and a second processing subsystem including multiple masters and multiple slaves. Further, a slave transaction ID for each master to any slave in the first processing subsystem and in the second processing subsystem is generated based on the computed slave transaction ID width. Furthermore, sparse connection information between the multiple masters and multiple slaves is determined via a first bus matrix in the first processing subsystem. A first optimized slave transaction ID for each master to any slave in the first processing subsystem is then generated by removing don't care bits in each generated slave transaction ID based on the sparse connection information.

Abstract: An illumination device comprises a plurality of light sources, light sequencing circuitry coupled to the light sources, a light guide structure for directing light from the plurality of light sources over a surface of a display screen to be illuminated, and a user interface for providing control input to the light sequencing circuitry. The light sequencing circuitry comprises a logic state machine responsive to the control input to select one of a plurality of available sequencing modes for the plurality of light sources, a code generator operative to generate output signals controlling respective ones of the light sources responsive to the selected one of the sequencing modes, and timing circuitry for defining timing intervals for processing of the control input by the logic state machine to determine the selected one of the sequencing modes and for generation of the corresponding output signals by the code generator.

Abstract: An integrated circuit chip that supports stored-pattern (SP) logic built-in self-testing (LBIST) includes a device under test (DUT) and a test controller. System-level SP LBIST testing is performed using an external, system ATE (automated test equipment) that transmits test input data to the test controller for application to the DUT, which generates test output data that is transmitted from the test controller to the system ATE, which performs golden signature comparisons on the test output data. During system-level DUT testing, all communications between the system ATE and the chip are via a single interface, such as a conventional, serial JTAG port.

Abstract: An iterative PCCC encoder includes a first delay line operative to receive at least one input data sample and to generate a plurality of delayed samples as a function of the input data sample. The encoder further includes a second delay line including a plurality of delay elements connected in a series configuration. An input of a first one of the delay elements is adapted to receive a sum of first and second signals, the first signal generated as a sum of the input data sample and at least one of the delayed samples, and the second signal generated as an output of a single one of the delay elements. A third delay line in the encoder is operative to generate an output data sample as a function of the sum of the first and second signals and a delayed version of the sum of the first and second signals.

Abstract: In described embodiments, a Floating Tap, Feed Forward Equalizer (FT-FFE) achieves performance comparable to a full size, long FFE when equalizing wire line channels in, for example, SerDes receivers. A FT-FFE might be employed as a standalone datapath equalizer, or might be employed in conjunction with other equalization techniques.

Abstract: A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA); associating an identifier with each cache entry in the subset of cache entries, the identifier indicating whether the cache entry comprises data that has been loaded using FA; and implementing a cache replacement policy for controlling replacement of at least a given cache entry in the data cache with a new cache entry as a function of the identifier associated with the given cache entry.

Abstract: A method of forming an electronic device provides an electronic device substrate having a solder bump pad located thereover. A nickel-containing layer is located over the solder bump pad. A copper-containing layer is formed on the nickel-containing layer prior to subjecting the electronic device to a reflow process.

Abstract: A storage medium for use in a computer to develop a circuit design. The storage medium recording a software tool that may be readable and executable by the computer. The software tool generally includes the steps of (A) receiving a first user input that identifies a specific cell of a plurality of existing cells in the circuit design, the specific cell having a timing characteristic, (B) generating a replacement display corresponding to the specific cell, the replacement display comprising a plurality of alternate cells suitable to replace the specific cell, each of the alternate cells having a different value associated with the timing characteristic of the specific cell, (C) receiving a second user input that identifies a replacement cell of the alternate cells and (D) automatically generating a first engineering change order to replace the specific cell with the replacement cell.

Abstract: Methods and structure are disclosed for improved processing of fast path I/O requests in a storage controller utilizing version information embedded in the fast path I/O requests. The version information allows the storage controller to determine if the mapping information utilized by the host system in generating a fast path I/O request specifies the mapping information utilized by the storage controller. The controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing software stack for processing I/O requests from a host system directed to a logical volume. If the mapping information utilized by the host does not match the mapping information utilized by the storage controller, fast path I/O requests are transferred to the I/O request processing stack for subsequent processing.

Abstract: Methods and structure for diagnosing errors in the initialization of DDR memory “on board” a storage controller or a storage expander are presented herein. The features and aspects discussed herein allow for the debugging of the DDR memory initialization. A memory diagnostic system is operable on a storage controller and includes an initialization module in communication with a firmware module of the storage controller. The memory diagnostic system is adapted to initialize a Double Date Rate (DDR) memory of the storage controller. The memory diagnostic system also includes an application programming interface adapted to retrieve initialization information from the initialization module and transfer the initialization information to a debug system via a direct communication link between the application programming interface and the debug system to diagnose the initialization of the DDR memory and to debug the initialization module based on the initialization information.

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

Abstract: Described embodiments provide a media controller that performs error correction on data read from a solid-state media. The media controller receives a read operation from a host device to read one or more given read units of the solid-state media. The media controller reads the data for the corresponding read units from the solid-state media employing initial values for one or more read threshold voltages. Only if a disparity between an actual number of bits at a given logic level included in the read data and an expected number of bits at the given logic level included in the read data has not reached a predetermined threshold, the media controller decodes the read data and provides the decoded data to the host device.

Abstract: The invention may be embodied in a network resistor model analysis tool for an Electrical Rule Checking (ERC) system. The network resistor model analysis tool typically includes, but need not be limited to, (i) a recursive, deterministic resistor path algorithm that identifies all valid resistor paths from a start net to a stopping net in a netlist corresponding to an analog circuit, (ii) a programming representation algorithm complete for representing the resistor paths in a programmatic format accessible through an application program interface, and (iii) a recursive, deterministic resistance value algorithm that solves the programmatically represented network to determine a total resistance value for each valid path and each resistor leg in each valid path.

Abstract: One embodiment is a method for booting a bootable virtual storage appliance on a virtualized server platform. One such method comprises: providing a virtual storage appliance on a server platform, the virtual storage appliance configured to manage a disk array comprising a plurality of disks, and wherein at least one of the disks comprises a hidden boot partition having a boot console; powering up the server platform; loading boot code on the server platform; loading the boot console from the hidden boot partition; and the boot console loading boot components for a virtualization environment.

Abstract: Various embodiments of the present invention provide systems and methods for updating detector parameters in a data processing circuit. For example, a data processing circuit is disclosed that includes a first detector circuit, a second detector circuit, and a calibration circuit. The first detector circuit is operable to receive a first data set and to apply a data detection algorithm to the first data set, and the second detector circuit is operable to receive a second data set and to apply the data detection algorithm to the second data set. The calibration circuit is operable to calculate a data detection parameter based upon a third data set. The data detection parameter is used by the first detector circuit in applying the data detection algorithm to the first data set during a period that the data detection parameter is used by the second detector circuit in applying the data detection algorithm to the second data set.

Abstract: Disclosed is a remote communication system and method. A remote communication system includes a digital protection relay and a remote monitoring system. The digital protection relay stores and maintains fault indices for identifying a predetermined number of faults that have occurred, fault time tags corresponding to the fault indices and fault data corresponding to the fault indices. The remote monitoring system sets a fault index, a fault time tag, a fault data block size to be communicated at a time and a fault data block index for specifying a fault data block to be communicated, and requests the digital protection relay of a fault data block.

Abstract: Disclosed is an electronic magnetic contactor, the contactor including: an operation power supply unit inputting an operation power; an electronic switch driving unit receiving a power from the operation power supply unit to drive a power supply of a load; a switching unit switched by a pulse signal to drive the electronic switch driving unit; an operation state determination unit determining whether the electronic magnetic contactor is in an opened state or in a closed state; an input voltage sensing unit sensing an amplitude of an input voltage supplied from the operation power supply unit; and an input signal generation unit generating an input signal for determining whether the electronic magnetic contactor is inputted based on determined state by the operation state determination unit and the sensed amplitude by the input voltage sensing unit.