Abstract: An apparatus including a processor, a computer readable storage medium, and a lookup memory. The computer readable storage medium generally contains computer executable instruction that when executed by the processor perform operations involving fixed point multiplication. The lookup memory generally stores values used in the fixed point multiplication. The values stored in the lookup memory are approximated based upon a predetermined value to prevent overflow in the fixed point multiplication.

Abstract: A method of verifying a password and methods of encryption and decryption using a key generated from a one-time pad. In one embodiment, the method of verifying includes: (1) receiving a password attempt, (2) retrieving a pointer from memory, (3) searching a one-time pad based on the pointer to retrieve a password, (4) comparing the password attempt with the password and (5) generating a new pointer if the password attempt matches the password.

Abstract: Described embodiments provide for arbitrating between nodes of scheduling hierarchy of a network processor. A traffic manager generates a tree scheduling hierarchy having a root scheduler and N scheduler levels. The network processor generates tasks corresponding to received packets. The traffic manager queues the received task in an associated queue of the scheduling hierarchy. The root scheduler performs smooth deficit weighted round robin (SDWRR) arbitration between each child node of the root scheduler. The SDWRR arbitration includes checking one or more status indicators of each child node of the given scheduler and selecting, based on the status indicators, a first active child node of the scheduler and updating the one or more status indicators corresponding to the selected child node. Thus, a task is scheduled for transmission by the traffic manager every cycle of the network processor.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, a data processing system is disclosed that includes: a data detector circuit, a low density parity check data decoder circuit, and a processing circuit. The processing circuit is operable to: reconstitute a second encoded sub-codeword from a combination of data including the first encoded sub-codeword and the composite sub-codeword; and correct an error in one of the first encoded sub-codeword and the second encoded sub-codeword based at least in part on a combination of the first encoded sub-codeword, the second encoded sub-codeword, and the composite sub-codeword.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having scan cells. The scan test circuitry further comprises transition launch mode selection circuitry configured to provide independent selection between multiple transition launch modes for each of a plurality of clock domains of the integrated circuit. The multiple transition launch modes may include, for example, at least a launch-on-shift mode and a launch-on-capture mode. These transition launch modes provide different manners of launching a given signal transition via at least one of the scan cells in a corresponding one of the clock domains. The transition launch mode selection circuitry may be configured to generate from a common shift enable signal multiple independently controllable shift enable signals for respective ones of the clock domains of the integrated circuit.

Abstract: An I/O scheduler and a method for scheduling I/O requests to a solid-state drive (SSD) is disclosed. The I/O scheduler in accordance with the present disclosure bundles the write requests in such a form that the write requests in each bundle goes into one SSD block. Bundling the write requests in accordance with the present disclosure reduces write amplification and increases system performance. The I/O scheduler in accordance with the present disclosure also helps increasing the life of the SSDs.

Abstract: Hardware-based methods and apparatus are provided for inter-track interference mitigation in magnetic recording systems using averaged values. Inter-track interference (ITI) is mitigated in a magnetic recording system by obtaining ITI cancellation data; and providing the ITI cancellation data for ITI mitigation, wherein the ITI mitigation is performed in combination with an averaging procedure for one or more of ITI mitigation of averaged data and averaging of ITI mitigated data. The sector is optionally decoded using the ITI mitigated samples. Samples for one or more side track sectors can also be averaged. The averaged side track samples can be provided as ITI cancellation data for ITI mitigation. The averaging procedure optionally applies a scaling factor to each read value.

Abstract: The disclosure provides instantaneous, vertical online capacity expansion (OCE) for redundant (e.g., RAID-5, RAID-6) and non-redundant (e.g., RAID-0) arrays. The new OCE technique implements vertical expansion instead of the horizontal expansion techniques implemented in current OCE techniques. The vertical expansion treats any new addition of storage as an extension of the capacity of the preexisting physical drives in order to avoid having to rewrite the data blocks of the original, preexisting storage devices. Vertical RAID expansion is implemented by installing one or more new physical storage devices in a device or partition configuration that corresponds to the physical configuration of the preexisting volume and loading new metadata received through the user interface into the firmware of the RAID controller to define the configuration of the expanded volume.

Abstract: Methods and structure for determining compatibility between a pair of SAS devices for support of super-standard features of the devices. Features and aspects hereof provide for exchange of information between a first and second SAS device using SAS protocol in non-standard manners. The exchanges are designed to exchange information between compatible, enhanced device without causing protocol violation errors in either the first or second devices. The information exchanged represents super-standard features supported by each device. Mutually supported super-standard features are enabled for further communications between the devices. If no super-standard features are mutually supported or if the second device is non-enhanced, no super-standard features are enabled in further communications between the devices.

Abstract: Higher-level redundancy information computation enables a Solid-State Disk (SSD) controller to provide higher-level redundancy capabilities to maintain reliable operation in a context of failures of non-volatile (e.g. flash) memory elements during operation of an SSD. A first portion of higher-level redundancy information is computed using parity coding via an XOR of all pages in a portion of data to be protected by the higher-level redundancy information. A second portion of the higher-level redundancy information is computed using a weighted-sum technique, each page in the portion being assigned a unique non-zero “index” as a weight when computing the weighted-sum. Arithmetic is performed over a finite field (such as a Galois Field). The portions of the higher-level redundancy information are computable in any order, such as an order based on order of read operation completion of non-volatile memory elements.

Abstract: Methods and structure are disclosed for improved processing of fast path I/O requests in a storage controller utilizing version information embedded in the fast path I/O requests. The version information allows the storage controller to determine if the mapping information utilized by the host system in generating a fast path I/O request specifies the mapping information utilized by the storage controller. The controller comprises a fast path I/O request processing circuit tightly coupled with host system drivers for fast processing of requests directed to storage devices of a logical volume. The controller also comprises a logical volume I/O processing software stack for processing I/O requests from a host system directed to a logical volume. If the mapping information utilized by the host does not match the mapping information utilized by the storage controller, fast path I/O requests are transferred to the I/O request processing stack for subsequent processing.

Abstract: Multi-layer in integrated transmission line circuits are provided having improved signal loss characteristics. A multi-layer integrated transmission line circuit, such as a stripline circuit or a microstrip circuit, comprises at least one reference layer; at least one conducting layer having one or more conducting strips, wherein the at least one conducting layer is separated from the at least one reference layer by a substrate; and at least one additional layer positioned between the at least one conducting layer and the at least one reference layer. The multi-layer integrated transmission line circuit may also comprise a dielectric insulating material, such as an organic material or a ceramic material. The additional layers increase a dielectric thickness of the multi-layer integrated transmission line circuit to reduce dielectric losses.

Abstract: An integrated circuit power grid is provided with improved routing resources and bypass capacitance. A power grid for an integrated circuit comprises a plurality of thick metal layers having a plurality of metal traces, wherein at least one of the thick metal layers has a lower pitch than a substantial maximum pitch allowed under the design rules for a given integrated circuit fabrication technology. A power grid for an integrated circuit can also comprise a plurality of thin metal layers having a plurality of metal traces, wherein a plurality of the metal traces on different thin metal layers are connected by at least one via, wherein the at least one via is substantially surrounded by a metal trace on at least one thin metal level connected to a different power supply voltage than a power supply of one or more additional thin metal levels. The via can be positioned, for example, at an intersection of a given standard cell row and a given vertical strap.

Abstract: A method and apparatus are provided for mapping addresses between one or more slave devices and at least one corresponding master device in a multilayer interconnect system including a plurality of bus matrices for interfacing between the one or more slave devices and the master device. The method and apparatus are operative for receiving an address map corresponding to the system, receiving information regarding connectivity of one or more slave devices through at least one of the bus matrices, determining whether the master device has more than one default slave unit associated therewith, and, when the master device has more than one default slave unit associated therewith, generating first and second address mappings and configuring the system to have no more than one default slave unit per master device.

Abstract: A lighting device having a support module supporting LEDs and having an outer perimeter defining a curved portion, and a housing with an inner surface having a curved portion configured to receive the curved portion of the support module to enable the disk to be aimed, while the curved portions of the disk and housing remain in contact. Optional adjustment means facilitate aiming of the support module without the need to open the sealed LED module.

Abstract: For a solid-insulated switchgear in which a main circuit switching mechanism and a ground circuit switching mechanism are provided laterally, and there is disclosed an interlock apparatus for the solid-insulated switchgear comprising a first interlock mechanism connected to a switching shaft of the ground circuit switching mechanism to press the on shaft of the main circuit switching mechanism to be at the locking position or release the on shaft of the main circuit switching mechanism; and a second interlock mechanism connected to the switching shaft of the main circuit switching mechanism in an interlocking manner to press the on shaft of the ground circuit switching mechanism to be at the locking position or release the on shaft of the ground circuit switching mechanism.

Abstract: A method for designing an integrated circuit is disclosed. The method generally comprises the steps of (A) splitting a design layout of the integrated circuit into a plurality of tiles, (B) adding a plurality of tie-to cells to the design layout, wherein at least one of the tie-to cells generating a tie-to signal at a particular logical level is added into each of the tiles having at least one gate with an input fixed to the particular logical level and (C) routing the tie-to signal to each of the inputs within each of the tiles.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: A semiconductor platform for implementing multiple-frequency operations includes multiple physical resources comprising embedded functions and a configurable transistor fabric. The transistor fabric includes at least first and second portions, the first portion being programmable to instantiate a first function having higher frequency operations than the second portion. The platform further includes multiple logical resources corresponding to the physical resources of the semiconductor platform and a configurable power mesh to support multiple frequency operations configurable from the transistor fabric. The power mesh includes at least first and second configurable grids. The first configurable grid is operable at a different frequency than the second configurable grid. The power mesh is modifiable, as a function of a desired performance of a customer's requirements, in a vicinity of the first portion of the configurable transistor fabric to support the first function having higher frequency operations.