Abstract: A method of subtracting floating-point numbers includes determining whether a first sign associated with a first floating-point number is unequal to a second sign associated with a second floating-point number, determining whether a first exponent associated with the first floating-point number is less than a second exponent associated with the second floating-point number, negating a first mantissa associated with the first floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent, and adding the first mantissa to a second mantissa associated with the second floating-point number when the first sign is unequal to the second sign and determining that the first exponent is less than the second exponent. Embodiments of a corresponding computer-readable medium and device are also provided.

Abstract: Disclosed is a method and SAS controller that abstract access from virtual machines operating on a host system to SAS physical devices connected to the SAS controller without a routing table for port-to-port messaging on the SAS controller. An embodiment may create a virtual expander for each physical port of the SAS controller and further create virtual ports within the virtual expanders to provide abstracted access to SAS physical devices for the virtual machines. The SAS physical devices may be replicated/cloned within the virtual ports. Each replicated/cloned SAS physical device may be assigned a unique SAS address for the SAS controller. If a physical expander that supports zoning is connected to a SAS controller port, an embodiment may further selectively replicate/clone the SAS physical devices for a virtual port based on whether or not a SAS physical device is included in a zoning group associated with the virtual port.

Abstract: A gate driving apparatus according to the embodiment includes a first switching device, a second switching device that outputs a signal to charge a capacitance of the first switching device, a third switching device connected in parallel to the second switching device to prevent a drop of a voltage output from the second switching device, and a fourth switching device that outputs a signal to discharge the capacitance of the first switching device. An NMOS transistor is used as a main switching device and a PMOS transistor connected in parallel to the NMOS transistor is used as a sub-switching device, so that the chip size is reduced without dropping the output voltage of the gate driving apparatus. The loss of the switching device is prevented by preventing the output voltage of the gate driving apparatus from being dropped.

Abstract: Methods and structure for masking of logical unit numbers (LUNs) within a switching device coupled with one or more storage enclosures. Each storage enclosure defines one or more logical volumes each identified by a LUN within the storage enclosures. The switching device gathers LUN definition information regarding each LUN defined by each storage enclosure coupled with the switching device. LUN access permission information may be provided by an administrative node/user defining a level of access permitted or denied for each host system for each LUN for each storage enclosure. The switching device then intercepts a REPORT LUNS command from any host directed to a storage enclosure and responds with only those LUNs to which the requesting host system has permitted access. Further, any other SCSI command intercepted at the switching device directed to a LUN to which the host system does not have access is modified to identify an invalid LUN.

Abstract: A digital protection relay is provided. An amplification factor is differently applied such that loss of a quantity of light with respect to an input signal is compensated for according to a length of an optical fiber cable for a point sensor. Thus, an occurrence of an arc can be more accurately detected, whereby power facilities and humans can be optimally protected from an arc accident.

Abstract: A method of delivering a therapeutic substance to tissue comprises delivering the therapeutic substance and nanoparticles to the tissue, the nanoparticles having a diameter in the range from 10 to 1000 nm and surface features having a depth in the range from 5 to 50 nm, and insonating the tissue with pressure waves. Corresponding particles, and associated methods of controlling and imaging the treatment and delivery are also disclosed.

Abstract: Disclosed is a system for acquiring and controlling information of power energy production, power transmission, and power consumption by storing information of circuit breakers, switches, power generators, power transmission lines, and transformers in the database, and a method of controlling the same. The method includes acquiring data from a remote control system, comparing the acquired data with data that are previously stored in a database, calculating an estimation value of data that are not acquired according to a comparison result, and performing fault current analysis or contingency analysis according to the calculated estimation value to calculate a rated capacity of a circuit breaker.

Abstract: In one embodiment, the invention is a method for performing preamble detection in a wireless communication network. The method performs a first dwell, wherein non-overlapping chunks of received data are processed to generate partial correlation values for each possible combination of a signature code and delay. Candidate selection is performed by comparing each of the partial correlation values to a candidate-selection threshold. For each detected candidate, the chunks of received data are processed to generate full correlation values. Each full correlation value is then compared to a preamble-detection threshold to detect a transmitted signature. Generating full correlation values for only the selected candidates reduces the computation complexity over prior-art methods that generate full correlation values for all signatures at all delays.

Abstract: Systems and methods for management of replicated storage. Features and aspects hereof provide management of data replication among a plurality of storage systems in a manner substantially transparent to host systems attached to the storage systems. The storage systems are coupled to one another through a replication link. One storage systems is designated the primary storage system and all others are designated secondary storage systems. A common logical volume is defined with a common logical volume device identifier used by all of the replicating storage systems of a replication group and their respective attached host systems. The primary storage system processes I/O requests directed to the logical volume by accessing its physical storage volume and forwarding the request to be replicated to all secondary storage systems over the replication link. Secondary storage systems process I/O requests by shipping them over the replication link to the primary storage system for processing.

Abstract: A method includes applying a write Input/Output (I/O) queue interval to a Logical Unit (LU) member of a consistency group (CG). The method also includes marking each write I/O with a timestamp and suspending I/O from the participating storage array to the LU member of the CG upon the participating storage array receiving a snapshot request from a master storage array. The method further includes determining whether the snapshot request timestamp is within the write I/O queue interval of the participating storage array.

Abstract: Various embodiments of the present invention provide systems and methods for sequence detection. As an example, a method for data detection is disclosed that includes: receiving a series of data samples at a detector circuit; multiplying a portion of the series of data samples by a first correlator value corresponding to a first binary transition to yield a first value; multiplying the portion of the series of data samples by a second correlator value corresponding to a second binary transition to yield a second value; adding the first value to a prior state value to yield a first interim value; adding the second value to the prior state value to yield a second interim value; and selecting the larger of the first interim value and the second interim value to yield a surviving interim value.

Abstract: Disclosed herein is a multi-clock interface, an integrated circuit and a module thereof having the multi-clock interface and a library having cells corresponding to the above noted circuitry. In one embodiment the multi-clock interface includes: (1) a multi-clock reset synchronizer configured to receive a first external clock signal and a second external clock signal that is a multiple of the first clock signal, the reset synchronizer configured to synchronize a reset of both the first and second external clock signals and based thereon generate a reset release signal and (2) a multi-phase clock generator configured to receive the reset release signal and the second clock signal, the multi-phase clock generator configured to generate multiple clock phases from the second clock signal based on the reset release signal.

Abstract: Various embodiments of the present invention provide single-ended and differential current drivers for heat assisted magnetic recording and other applications. For example, a current driver is disclosed that includes an upper output terminal and lower output terminal, a number of current switches operable to selectively contribute electrical currents through the upper and lower output terminals, a control input for each of the current switches operable to control the electrical currents, and a voltage supply operable to establish a voltage across the upper and output terminals.

Abstract: Various embodiments of the present invention provide systems and methods for generating a code format. One method discussed includes: receiving a first matrix having a row width and a column height that is greater than one; incorporating a circulant into a first column of the first matrix; testing the first column for trapping sets, wherein at least one trapping set is identified; selecting a value to mitigate the identified trapping set; and augmenting the first matrix with a second matrix to yield a composite matrix. The second matrix has the selected value in the first column, and wherein the identified trapping set is mitigated.

Abstract: Disclosed is a system and method that resolves a mismatch between software versions executing on redundant controllers. A mismatch between a first software version executing on a first redundant controller and a second software version executing on a second redundant controller is identified. By comparing software version identifiers associated with the first software version, the second software version, and a stored system software identifier, a preferred software version is selected. The preferred software version is copied from a controller running the preferred software version to the other controllers.

Abstract: A method and apparatus are provided for using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for detecting patterns in a data stream.

Abstract: A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.

Abstract: Various embodiments of the present invention provide systems and methods for sync mark detection. As an example, a sync mark detection circuit is discussed that includes a storage circuit, a plurality of noise predictive filter circuits, and a controller circuit. The storage circuit is operable to store a data input as a stored input. The plurality of noise predictive filters are operable to receive a processing input. At least one of the noise predictive filters is selectably modifiable to either increase the probability of finding a sync mark in the processing input or to maintain a baseline probability of finding the sync mark in the processing input. The controller circuit is operable to determine an operational mode that may be a standard operational mode, a bit flipping mode, or a filter modification mode.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. As an example, a data processing circuit is disclosed that includes an equalizer circuit, a noise predictive filter circuit, a data detector circuit, a data reconstruction circuit, and an adaptation circuit. The equalizer circuit is operable to receive a data input and to provide an equalized output based at least in part on an equalizer coefficient. The noise predictive filter circuit is operable to receive the equalized output and to provide a noise whitened output based at least in part on a noise predictive filter coefficient. The data detector circuit is operable to apply a data detection algorithm to the noise whitened output to yield a detected output. The data reconstruction circuit is operable to receive the detected output and to provide a reconstructed output corresponding to the equalized output based at least in part on a target polynomial.