Abstract: Various embodiments of the present invention provide systems and methods for min-sum based decoding of non-binary LDPC codes. For example, a non-binary low density parity check data decoding system is discussed that includes a variable node processor and a check node processor. The variable node processor is operable to generate variable node to check node message vectors and to calculate perceived values based on check node to variable node message vectors. The check node processor is operable to generate the check node to variable node message vectors and to calculate checksums based on variable node to check node message vectors. The check node processor includes a minimum and subminimum finder circuit operable to process a plurality of sub-messages in each variable node to check node message vector. The check node processor also includes a select and combine circuit operable to combine an output of the minimum and subminimum finder circuit to generate the check node to variable node message vectors.

Abstract: An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises at least one scan chain having a plurality of scan cells, with the scan chain being configured to operate as a serial shift register in a scan shift mode of operation and to capture functional data from at least a portion of the additional circuitry in a functional mode of operation. At least a given one of the scan cells of the scan chain comprises output control circuitry which is configured to disable a functional data output of the scan cell in the scan shift mode of operation and to disable a scan output of the scan cell in the functional mode of operation.

Abstract: Described embodiments schedule packets for transmission by a network processor. A traffic manager generates a scheduling hierarchy having a root scheduler and N levels. The network processor generates tasks corresponding to received packets. The traffic manager enqueues tasks in an associated queue. The queue has a corresponding level M, with a corresponding parent scheduler at each of M?1 levels in the scheduling hierarchy, where M is less than or equal to N. In a single scheduling cycle, a parent scheduler selects a child node to transmit one or more tasks, and the child node responds whether the scheduling is accepted, and if so, with a number of tasks for scheduling. Starting at the parent scheduler and iteratively repeating at each level until reaching the root scheduler, statistics corresponding to the selected node are updated. Output packets corresponding to the scheduled tasks are transmitted, thereby achieving a superscalar task scheduling throughput.

Abstract: A method is disclosed for updating parity information in a RAID 6 system wherein only one parity block is read during each write operation. Both parity blocks may be updated from the new data, the data being overwritten and either of the old blocks of parity information. A method for load balancing in a RAID 6 system using this method is also disclosed.

Abstract: Various embodiments of the present invention provide systems and methods for data writing. As an example, a heat assisted loopback circuit is discussed that includes: a read circuit, a magnetic write circuit, a heat write circuit, and a loopback circuit. The read circuit is operable to sense data from a storage medium, and to provide the sensed data as a read output. The magnetic write circuit is operable to provide a write output corresponding to an excitation signal of a write head. The heat write circuit is operable to provide a heat output corresponding to an excitation signal of a heat source. The loopback circuit is operable to selectively couple a derivative of the heat output to the read output and to selectively couple a derivative of the write output to the read output.

Abstract: A method for computing and storing parity information in a RAID system includes dividing each segment in a stripe into a data block and a parity block, and storing in each parity block, parity information for a limited number of other data blocks in the stripe. A method for rebuilding data in a RAID system includes rebuilding the data from parity information and storing the rebuilt data on reserve portions of the remaining disks in the system.

Abstract: An integrated circuit comprises a memory or other type of circuit core having an input interface and an output interface, built-in self-test circuitry configured for testing of the circuit core between its input and output interfaces in a built-in self-test mode of operation, and at least one scan chain having a plurality of scan cells. The scan cells of the scan chain are coupled to respective signal lines at the input and output interfaces and configured to allow capture of functional signal values from those signal lines in a functional mode of operation and shifting out of the captured functional signal values in a scan shift mode of operation. This allows detection of faults associated with functional paths of the interface that would otherwise not be detectable using the built-in self-test circuitry.

Abstract: Disclosed are an apparatus for alarming an inverter status and an apparatus for analyzing a motor status in a mobile terminal. The apparatus for analyzing a motor status in a mobile terminal includes: a first recognition unit configured to recognize vibrations of a motor contacting thereto, and providing the vibrations to a controller; a second recognition unit configured to recognize sound of the motor, and providing the sound to the controller; and the controller configured to analyze a frequency from the vibrations and sound of the motor, to check a change of the vibrations, and thus to obtain an analysis result on a status of the motor.

Abstract: A hard disk drive or other disk-based storage device comprises a storage disk, a write head configured to write data to the disk, and control circuitry coupled to the write head. The control circuitry comprises a write driver and degauss circuitry associated with the write driver. The degauss circuitry is configured to control a degauss signal waveform to be applied to the write head by the write driver, and comprises separate amplitude envelope control mechanisms for steady state and overshoot portions of the degauss signal waveform. The separate amplitude envelope control mechanisms may comprise, for example, separate steady state and overshoot controllers for controlling the amplitude envelope decay rates of the respective steady state and overshoot portions of the degauss signal waveform over the plurality of pulses.

Abstract: A system for detecting a partial discharge signal comprises a signal detecting unit configured to detect a partial discharge signal and a noise signal of an electric power equipment; a communicating unit configured to transmit the detected partial discharge signal and noise signal through a communication network; a control unit configured to determine a level of risk of the partial discharge signal on the basis of analysis results of a partial discharge signal trend analysis algorithm and a partial discharge signal pattern analysis algorithm when the partial discharge signal transmitted through the communication network is greater than the noise signal; and a display unit configured to display the determined level of risk.

Abstract: In one embodiment, a scheme for reliably reading data values, such as rapidly-changing counter values, from a memory location. Instead of performing a single read operation, a set of N consecutive read operations is performed to obtain a set of N samples. Since, for counter values and the like, the frequency of occurrence of out-of-sequence values is relatively low, it is expected that a majority of the N samples will be in sequence. Of these N samples, the largest subset of monotonically-increasing values is selected. The median value of this subset of monotonically non-decreasing values is returned as a reliable result of the read operation.

Abstract: A memory device includes a memory array comprising a plurality of memory cells. At least one of the memory cells comprises a pair of cross-coupled inverters, and a plurality of ports, including at least one write port. A given write port comprises at least one drive control circuit having an output coupled to respective gate terminals of both a write assist transistor and a drive transistor, with the write assist transistor being arranged in series with one of a pull-up and a pull-down path of a corresponding one of the inverters, and the drive transistor being configured to hold one of the internal nodes at a designated logic level in conjunction with a write operation. First and second drive control circuits of this type may generate complementary control signals for application to respective pairs of write assist and drive transistors associated with respective ones of the inverters.

Abstract: Disclosed is a load compensating device in railway vehicles, the device including a pressure sensor detecting an air spring pressure in response to loads of the vehicles, an estimation unit outputting an estimated railway vehicle load by estimating each load of a plurality of railway vehicles, and a detection unit outputting a railway vehicle load by detection of fault in the pressure sensor.

Abstract: The invention provides for SSD cache expansion by assigning all excess overprovisioned space (OP) above a level of advertised SSD memory to SSD cache. As additional SSD memory is needed to provide the advertised SSD memory, an offsetting portion of the OP is reassigned from excess overprovisioned space to the SSD cache. In this manner, the advertised SSD memory is maintained while continuously allocating all available excess OP to cache. The result is that all of the available SSD memory is allocated to cache, a portion to maintain the advertised SSD memory and the balance as excess OP allocated to cache. This eliminates idle OP in the SSD allocation.

Abstract: An apparatus for encoding RFID tag is disclosed, the apparatus including an RFID reader managing an encoding section for encoding tag information on a tag in a case a trigger signal is received from a PLC and an inspection section for inspecting the encoded tag information, whereby productivity can be enhanced and a high speed encoding can be realized.

Abstract: Methods and structure for transferring additional parameters through a communication interface with limited parameter passing features. Features and aspects hereof provide for generating and transmitting multiple related commands from an initiator device to a target device where one or more initial commands provide additional parameters. The additional parameters are utilized in processing the last of the multiple commands to actually perform a desired data transfer. The initial commands and the data transfer command may all be associated by encoding of a common tag or sub-tag value in each command. The initial commands may be read/write commands having a zero data transfer length. The associated data transfer command may be a read/write command having a non-zero data transfer length. The initial commands each provide one or more additional parameters for processing the data transfer command in addition to the standard parameters that may be encoded in the data transfer command.

Abstract: Methods and structure for transferring administrative information through a communication interface. Features and aspects hereof provide for exchanging administrative information between an initiator device and a target device using read and write commands encoded with a reserved sub-tag value. In the context of a Serial Advanced Technology Attachment (SATA) system, a portion of a parameter (e.g., the LBA parameter) of a read or write command (a Native Command Queuing command) is defined to encode a sub-tag value. One or more sub-tag values are reserved to indicate that the corresponding read or write command is related to the exchange of administrative information rather than the reading or writing of data on a storage device. A parameter value encoded in the LBA field or data length field of the read or write command indicates administrative data to be returned to the initiator or to be updated within the target device.

Abstract: Disclosed is an electromagnetic switching apparatus capable of reducing noise occurring when a movable contact comes in contact with or is separated from a fixed contact, and capable of enhancing a function to extinguish arcs. The electromagnetic switching apparatus includes a fixed terminal fixed in a manner to penetrate through a housing, a fixed contact configured to approach to or to be separated from the fixed terminal, an elastic member fixed between the fixed terminal and the fixed contact, and providing an elastic force to a direction to separate the fixed contact from the fixed terminal, a movable contact configured to contact or to be separated from the fixed terminal, and a moving unit configured to move the movable contact so as to contact or to be separated from the fixed contact.

Abstract: Various embodiments of the present invention provide systems, methods and circuits for use of a memory system. As one example, an electronics system is disclosed that includes a memory bank, a memory access controller circuit, and an encoding circuit. The memory bank includes a plurality of multi-bit memory cells that each is operable to hold at least two bits. The memory access controller circuit is operable to determine a use frequency of a data set maintained in the memory bank. The encoding circuit is operable to encode the data set to yield an encoded output for writing to the memory bank. The encoding level for the data set is selected based at least in part on the use frequency of the data set.

Abstract: An apparatus including an adder, a delay line, and a first detector. The adder may be configured to generate an input signal in response to a received signal and a feedback signal. The feedback signal may include a contribution from each of a plurality of delayed versions of the input signal. The contribution from each of the plurality of delayed versions of the input signal may be determined by a respective weight value. The delay line may be configured to generate the plurality of delayed versions of the input signal. The first detector may be configured to recover a data sample from the input signal in response to a clock signal.