Abstract: The present disclosure provides a magnetic coil assembly for suppressing the generation of broken wire in a coil as well as reducing a winding time, the magnetic coil assembly according to the present disclosure comprise a bobbin; a magnetic coil wound around the bobbin; a pair of terminals fixedly installed at the bobbin; a first coil fixing protrusion portion extended from the terminal to fix a starting end portion of a first coil half which is a half of the entire length of the magnetic coil; a second coil fixing protrusion portion extended from the bobbin to fix a starting end portion of a second coil half which is the remaining half of the magnetic coil, and fix an terminal end portion of the first coil half; and a third coil fixing protrusion portion extended from the terminal to fix a terminal end portion of the second coil half.

Abstract: A method comprising the steps of (A) generating a code, (B) applying one or more constraint constructs to the code, (C) generating a coverage code and a second code in response to applying the constraint constructs to the code, (D) generating a third code in response to the code, and (E) generating one or more assembly language tests in response to the second code.

Abstract: Disclosed is an internal cable system that communicates signals in an electronic device. The system uses a printed circuit board with active circuits that is connected to a standard communication cable. The printed circuit board is exposed to air flow from the cooling system of the electronic device for proper operation of the active components of the active circuits on the printed circuit board. The standard cable may include a SCSI internal cable or other similar signal communication cables. Signal integrity is enhanced using the active circuits that are mounted on the printed circuit board. Power is supplied to the printed circuit board through inactive conductors in the cable or conductors that would otherwise be used for grounding.

Abstract: An apparatus comprising a control circuit, a buffer circuit and a memory. The control circuit may be configured to present a plurality of pairs of signals in response to (i) one or more input signals operating at a first data rate and (ii) an input clock signal operating at a second data rate. The second signal in each of the pairs comprises a clock signal operating at the second data rate. The buffer circuit may be configured to generate a buffered signal in response to each of the pairs of signals. Each of the buffered signals operates at the second data rate. The memory may be configured to read and write data at the second data rate in response to the buffered signals.

Abstract: A comparator determines the fidelity of a response vector received from a memory under test. The comparator includes a first logic gate configured to output a first value that is the logical OR of a first proper subset of bits of the response vector. A second logic gate is configured to output a second value that is the logical NAND of the proper subset of bits. A first multiplexer is configured to select between the first and second values based on the value of a first bit of a check vector corresponding to the response vector.

Abstract: Techniques are provided for identifying at least one aspect associated with a lifetime of each of a plurality of memory devices. Further, data is moved between the plurality of memory devices, based on the at least one aspect.

Abstract: Techniques are provided for prolonging a lifetime of memory by controlling operations that affect the lifetime of the memory. At least one aspect associated with the memory lifetime is identified and at least one of the operations is delayed, based on the at least one aspect. The operations include a write operation, an erase operation, a program operation, and/or any other operation that is capable of reducing the memory lifetime.

Abstract: A system, method, and computer program product are provided for sending de-allocation status information. In use, a de-allocation status of at least a portion of memory associated with a logical block address is determined. Additionally, de-allocation status information is generated, based on the determination. Furthermore, the de-allocation status information is sent to a device.

Abstract: The present invention is directed to a method for providing Quality Of Service (QoS)-based storage tiering and migration in a storage system. The method allows for configurable application data latency thresholds to be set on a per user basis and/or a per application basis so that a storage tiering mechanism and/or a storage migrating mechanism may be triggered for moving application data to a different class of storage.

Abstract: A hardware automated IO path, comprising a message transport unit for transporting an IO request to a local memory via a DMA operation and determining a LMID for associating with a request descriptor of the IO request; a fastpath engine for validating the request descriptor and creating a fastpath descriptor based on the request descriptor; a data access module for performing an IO operation based on the fastpath descriptor and posting a completion message into the fastpath completion queue upon a successful completion of the IO operation. The fastpath engine is further configured for: receiving the completion message, releasing the IO request stored in the local memory, and providing a reply message based on the completion message. The message transport unit is further configured for providing the reply message in response to the IO request.

Abstract: Techniques for writing data to different portions of storage devices based on write frequencies are disclosed. Frequencies of data writes to various portions of a memory are monitored. The memory includes various storage technologies. Each portion includes one of the storage technologies and has a respective lifetime. An order that the portions are written into and recycled is dynamically managed to equalize respective life expectancies of the portions in view of differences in endurance values of the portions, the monitored frequencies of data writes, and the lifetimes. In some embodiments, the storage technologies include Single-Level Cell (SLC) flash memory storage technology and Multi-Level Cell (MLC) flash memory storage technology. The SLC and MLC flash memory storage technologies are optionally integrated in one device. In some embodiments, the storage technologies include two or more different types of SLC flash memory storage technologies, optionally integrated in one device.

Abstract: Storage systems configured for improved N-way connectivity among all of a plurality of storage controllers and all of a plurality of storage devices in the system. All controllers of the storage system are coupled through a switched fabric communication medium to all of the storage devices of the storage system. Thus, the back-end interface of each storage controller of the storage system is used for all communications with any of the storage devices as well as for any communications among the controllers to coordinate the N-way distribution of stored data in a declustered RAID storage environment. This use of the back-end channel for all storage controller to storage device N-way connectivity as well as controller to controller N-way connectivity eliminates the need for a dedicated inter-controller interface for such N-way connectivity and eliminates the over-utilization of a front-end (e.g., network) communication path for providing N-way connectivity in the storage system.

Abstract: Disclosed is a method for sharing input/output ports among inverters. A sharing method by a master inverter according to the present disclosure is such that data to be outputted to an output port of a slave inverter is transmitted to the slave inverter where data inputted to input port of the slave inverter is received. Furthermore, a sharing method by the slave inverter is such that data transmitted along with a request frame is outputted to an output port in case of receiving the request frame requesting use of the output port from the master inverter, where data used by the master inverter among data received from input port is transmitted to the master inverter.

Abstract: A controller is provided that receives a single enclosure management (EM) serial bit stream from an expander or other device and divides the EM serial bit stream into multiple EM serial bit streams for delivery to multiple respective midplanes or backplanes. In this way, a separate EM serial bit stream is provided to each midplane or backplane without having to increase the number of ports that are available on the expander or other device that interfaces with the backplane or midplane.

Abstract: An electronic device includes a heat dissipating component located over a substrate. An isolation trench is formed in the substrate adjacent the component. A contact region of the substrate is bounded by the trench. An electrically isolated contact is located over and in contact with the contact region. The electrically isolated contact and the contact region provide a thermally conductive path to the substrate.

Abstract: The present disclosure is directed to a method for providing continuous data protection for a virtual volume (VV). The method may comprise conceptually dividing the VV into a plurality of same sized chunks; preserving contents of the VV at a specified time; creating a Point in Time (PiT) instance for the VV at the specified time, comprising: a PiT Temporary Virtual Volume (PTVV) for storing modifications to the VV subsequent to the specified time, wherein data stored in the PTVV is prohibited from been overwritten; a re-allocation table for providing read access to a most recent version of each of the plurality of chunks of the VV; and a Continuous Data Protection (CDP) log for providing read access to a historic version of a chunk stored in the PTVV; and updating the PiT instance when a chunk of the plurality of chunks of the VV is being modified.

Abstract: A method for deinterlacing a picture is disclosed. The method generally includes the steps of (A) generating a plurality of primary scores by searching along a plurality of primary angles for an edge in the picture proximate a location interlaced with a field of the picture, (B) generating a plurality of neighbor scores by searching for the edge along a plurality of neighbor angles proximate a particular angle of the primary angles corresponding to a particular score of the primary scores having a best value and (C) identifying a best score from a group of scores consisting of the particular score and the neighbor scores to generate an interpolated sample at the location.

Abstract: Methods and apparatus are provided for improved physical re-read operations in a hard disk drive. The disclosed methods and apparatus selectively retain data in a hard disk drive. A signal is read in an iterative read channel by assigning a reliability metric to each of a plurality of segments in a read signal; repeating the assigning step for a plurality of read operations; and selectively retaining the segments based on the assigned reliability metric. The read signal can be obtained by positioning a transducer over a storage media. The reliability metric may be based on soft bit decisions; log likelihood ratios or a noise estimation of a given segment.

Abstract: Embodiments of the invention include a method, apparatus and system for providing a Serial Attached SCSI (SAS) domain management application using a domain overlay architecture. The method includes comparing user constructs or data sets defining an existing domain overlay with device data that identifies various network devices in at least one SAS domain, and binding the existing domain overlay to an SAS domain if the existing domain overlay and the SAS domain are uniquely associated with one another. The method also includes creating a new domain overlay that is uniquely associated with an SAS domain for any SAS domain that is not bound to an existing domain overlay. A domain overlay and an SAS domain are not uniquely associated with one another unless the domain overlay references only network devices within the SAS domain and the network devices within the SAS domain are referenced only by the domain overlay.

Abstract: A method for reducing path delay sensitivity to temperature variation in a circuit is provided. The method includes the steps of: identifying at least one timing-critical path in the circuit, the path including a plurality of circuit cells coupled between an input and an output of the path; determining a temperature slope coefficient of the path; when the slope coefficient is negative, increasing the slope coefficient by controlling at least one characteristic of at least one of the cells in the path; and when the slope coefficient is positive, decreasing the slope coefficient by controlling at least one characteristic of at least one of the cells in the path.