Abstract: Systems and methods herein provide for protecting data using snapshots and images of those snapshots to quickly recreate data upon request. For example, a storage controller of a data storage system allocates a period of time between creating snapshots of data in a first storage volume of the data storage system. The controller then logs received write requests to the first storage volume and generates snapshot of data in the first storage volume based on the allocated period of time. Thereafter, the controller may receive a request to recreate data. The controller locates the snapshot in the first storage volume based on that request to recreate the data. In doing so, the controller generates a snapshot image in a second storage volume. The controller then retrieves logged write requests and applies them to the snapshot image to recreate the data in the second storage volume.

Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and single and dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Abstract: An MOS device includes a semiconductor layer of a first conductivity type and first and second source/drain regions of a second conductivity type formed in the semiconductor layer proximate an upper surface of the semiconductor layer. The first and second source/drain regions are spaced apart relative to one another. A gate is formed above and electrically isolated from the semiconductor layer, at least partially between the first and second source/drain regions. At least a given one of the first and second source/drain regions is configured having an effective width that is substantially greater than a width of a junction between the semiconductor layer and the given source/drain region.

Abstract: An apparatus and method are disclosed for maintaining consistent port and PHY configuration information in an SAS controller when connected SAS devices are rebooted, reset or otherwise temporarily disconnected. Configuration information is stored in non-volatile memory, and restored by a methodology to prevent port conflicts.

Abstract: Described embodiments provide logical-to-physical address translation for data stored on a storage device having sectors organized into blocks and superblocks. A flash translation layer maps a physical address in the storage device to a logical sector address. The logical sector address corresponds to mapping data that includes i) a page index, ii) a block index, and iii) a superblock number. The mapping data is stored in at least one summary page corresponding to the superblock containing the physical address. A block index and a page index of a next empty page in the superblock are stored in a page global directory corresponding to the superblock. A block index and a page index of the at least one summary page and the at least one active block table for each superblock are stored in at least one active block table of the storage device.

Abstract: Systems and methods for compressing state machine instructions are disclosed herein. In one embodiment, the method comprises associating input characters associated with states to respective indices, where each index comprises information indicative of a particular transition instruction.

Abstract: A lighting apparatus is shown and described. In one aspect, the lighting apparatus includes a light source, a plate, and frame. The light source can include one or more lighting elements that are in thermal communication with the light source. The plate can have a dissipative portion extending outward from a point of thermal communication between the plate and the light source. The frame can at least partially enclose the light source and may also be in thermal communication therewith.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to present a video signal and macroblock data in response to decoding one or more bins on a binary signal. The second circuit may be configured to, in parallel (i) generate the binary signal in response to a bitstream signal and an initial context information and (ii) calculate subsequent context information.

Abstract: A method of generating a floorplan layout of an integrated circuit (IC) that is amenable to implementation in a computer-aided design tool. The method is capable of performing placement and routing processing for the IC while requiring very little information about the specific circuitry used in various functional blocks of the IC. For example, at the time of the placement and routing processing, one or more functional blocks of the IC can be specified as empty functional blocks and/or functional blocks that are only partially rendered in gates.

Abstract: A spring housing unit connected to a switch actuator for a switchgear, which is compact and easily installed, the spring housing unit comprises a main spring housing configured as a hollow cylinder, having a flange portion formed at one end portion thereof to support one end portion of a spring, and accommodating the spring therein such that the spring is compressed or elongated; a sub-spring housing connected to the other end portion of the main spring housing such that it is separated therefrom; and a compressing cover insertedly positioned in the main spring housing and compressing the spring.

Abstract: Disclosed is a system and a method for controlling torque of induction motor in electric vehicle. The system and method for controlling torque of induction motor in electric vehicle according to the present disclosure has an advantageous effect in that torque control problems caused by saturation of magnetic flux, parameters of induction motor and changes in battery voltages during control of torque in the induction motor can be solved using a look-up table (a type of data table), thereby enhancing accuracy in torque control and improving travel performance and fuel efficiency of the electric vehicle.

Abstract: Methods and systems for data distribution may include, but are not limited to: receiving a request from a client device to store data on a distributed storage system; obtaining a hierarchical cluster map representing the distributed storage system; selecting an object at a hierarchical level of the cluster map; determining if the hierarchical level is a drive level; and adding a drive identifier associated with the object to a drive identifier array if the hierarchical level is the drive level.

Abstract: In order to provide a solution for performing priority arbitration, a mask and reset-mask are generated in concert with a priority arbitration scheme. A plurality of requestors may issue requests for a shared resource. The priority arbitration scheme may grant access to a single requestor for a single priority assignment period. The mask may assist the priority arbitration scheme to assign priority to the plurality of requestors by temporarily removing a subset of the plurality of requestors for a particular priority assignment period. If the mask allows for no allowable requestors during the priority assignment period, a reset-mask scheme is implemented to reset the mask to permit an increased number of requestors access to the priority arbitration scheme.

Abstract: A movable contactor assembly for a current limiting type circuit breaker comprises a movable contactor having a pair of curved protrusions having cam profiles, a shaft to rotatably support the movable contactor located therein, a pair of contact levers each having a contact surface contactable with the curved protrusion of the movable contactor and a pair of spring supporting recess portions and a pair of springs each having both end portions supported by the spring supporting recess portions, the pair of springs applying an elastic force as contact pressure for maintaining a contact state between the movable contactor and the stationary contactor when the movable contactor is located at the first position, and applying the elastic force in a direction to separate the movable contactor from the stationary contactor when the movable contactor is moved over a dead point while rotating toward the second position.

Abstract: An expander device and method for transmitting serial input/output (SIO) data between an initiator device and a plurality of target devices. The expander device includes a processor/controller configured to receive a master data stream from an initiator device and to transmit a returning master data stream to the initiator device. The expander device includes a plurality of target master ports coupled to the processor/controller and configured to transmit split data streams to corresponding target devices coupled thereto and to receive returning split data streams from the target devices. The processor/controller splits the master data stream, based on its data, into a plurality of split data streams, and directs the split data streams to the target master ports based on the data in the split data streams. The processor/controller also assembles a plurality of returning split data streams into the returning master data stream and transmits the returning master data stream to the initiator device.

Abstract: An apparatus including a processor and a memory. The processor may be configured to process pixel data comprising eight or more bits. For pixel data having bit-depths greater than eight bits, a number of most significant bits (MSBs) of a pixel are presented as a first byte and a number of least significant bits (LSBs) of the pixel are packed with LSBs from one or more other pixels into a second byte. The memory may be coupled to the processor and configured to store the first byte in response to a first pointer and the second byte in response to a second pointer. The first byte and the second byte are stored independently in the memory.

Abstract: An apparatus having a cache and a circuit. The cache may store old lines having old instructions. The circuit may (i) receive a first read command, (ii) fetch-ahead a new line having new instructions into a buffer sized to hold a single line, (iii) receive a second read command, (iv) present through a port a particular new instruction in response to both (a) a cache miss of the second read command and (b) a buffer hit of the second read command and (v) overwrite a particular old line with the new line in response to both (a) the cache miss of the second read command and (b) the buffer hit of the second read command such that (1) the first new line resides in all of the cache, the buffer and the memory and (2) the particular old line resides only in the memory.

Abstract: A system includes a data storage device, a controller coupled with the data storage device, a backup device coupled with the controller for backing up a modified portion of data and volatile memory metadata stored by the controller, and a backup power source for powering the controller. The controller includes a pre-specified region of volatile memory for storing backup device metadata for managing a modified portion of data, the metadata comprising one or more intents corresponding to modified data written back to the data storage device. The controller is configured to invalidate the one or more intents. During a restore operation, the controller is configured to store the backup device metadata in the pre-specified region of volatile memory when a charge on the backup power source is at least a minimum threshold charge and to store the updated backup device metadata in the backup device during an interruption of power.

Abstract: Disclosed is a trip device of a circuit breaker, the device including: a rectifying unit converting an AC (Alternating Current) voltage applied to the circuit breaker to a DC (Direct Current) voltage; a smoothing unit connected to the rectifying unit in parallel to mitigate ripples of the converted DC voltage; and a trip coil connected to the smoothing unit in parallel to determine whether to trip the circuit breaker.

Abstract: A method and apparatus configured to allow independent threads to communicate synchronously through a block of memory accessible to at least two independent threads for bi-directional communication. The method and apparatus simplify the conversion of computer code to a multi-threaded architecture by allowing threads to effectively interact through function calls and data returns.