Abstract: The present invention is directed to a circuit for managing data movement between an interface supporting the PLB6 bus protocol, an interface supporting the AMBA AXI bus protocol, and internal data arrays of a cache controller and/or on-chip memory peripheral. The circuit implements register file buffers for gathering data to bridge differences between the bus protocols and bus widths in a manner which addresses latency and performance concerns of the overall system.

Abstract: A bimetal assembly includes: a heater connected to a movable contact to be provided with power; and a bimetal having one end portion coupled to the heater and disposed to be spaced apart from the heater, wherein the heater includes: a coupling portion coupled to the bimetal; a separation portion spaced apart by a certain distance from the bimetal; and a connection portion connecting the coupling portion and the separation portion, wherein at least one projection is formed to be protruded from the separation portion toward the bimetal.

Abstract: In an exemplary computer system having one or more masters configured to the same slave memory using a protocol, such as the AMBA AXI protocol, a master provides an ID field to the memory as part of a data request, where the ID field has a line ID sub-field that represents a line ID value that uniquely identifies a particular cache line (or subset of cache lines) in the master, where the memory returns the line ID value back to the master along with the retrieved data. The master uses the line ID value to identify the cache line into which the retrieved data is to be stored. In this way, the master does not need to maintain a queue of address buffers to retain the addresses for data requests currently being processed, where the size of the queue limits the number of parallel in-service data requests by the master.

Abstract: In certain embodiments, a digital signal processor (DSP) has multiple arithmetic logic units and a register module. The DSP is adapted to generate a message digest H from a message M in accordance with the SHA-1 standard, where M includes N blocks M(i), i=1, . . . , N, and the processing of each block M(i) includes t iterations of processing words of message schedule {Wt}. In each iteration possible, the DSP uses free operations to precalculate Wt and working variable values for use in the next iteration. In addition, in each iteration possible, the DSP rotates the registers associated with particular working variables to reduce operations that merely copy unchanged values from one register to another.

Abstract: A method and controller device for supplying battery power to a virtualized storage environment having a storage controller with a virtual machine manager and a second virtual machine. In response to a battery engaged event, the first virtual machine manager enables the image of the second virtual machine to be shared with a new instance of the second virtual machine so that the image does not have to be loaded therein. The first virtual machine manager then creates the new virtual machine. The old virtual machine shuts down non-necessary hardware devices and sets necessary hardware devices to low power mode. During this time, the new virtual machine executes a backup specific start-of-day (SOD) initialization sequence. The method also synchronizes the new and old virtual machines. The method also initiates a cache memory backup operation upon synchronization of the new and old virtual machines and then shuts down the old virtual machine.

Abstract: A video transcoder is disclosed. The video transcoder generally comprises a processor and a video digital signal processor. The processor may be formed on a first die. The video digital signal processor may be formed on a second die and coupled to the processor. The video digital signal processor may have (i) a first module configured to perform a first operation in decoding an input video stream in a first format and (ii) a second module configured to perform a second operation in coding an output video stream in a second format, wherein the first operation and the second operation are performed in parallel.

Abstract: Various embodiments of the present invention provide systems and methods for data processing. For example, some embodiments of the present invention provide data processing circuits that include a variable gain amplifier, a gain circuit, and hybrid gain feedback combination circuit. The variable gain amplifier is operable to apply a gain to a data input corresponding to a gain feedback value and providing an amplified output. The gain circuit is operable to calculate a first algorithm error component and a second algorithm error component based at least in part on the amplified output. The hybrid gain feedback combination circuit is operable combine the first algorithm error component and the second algorithm error component to yield the gain feedback value when the data input includes a synchronization pattern.

Abstract: A syndrome calculator receives an input codeword and calculates a first set of syndromes. A syndrome transform receives the first set of syndromes having and determines a second set of syndromes. The second set of syndromes is based on the first set of syndromes. The second set of syndromes has number of syndromes that is less than the number of syndromes in the first set of syndromes. A key equation solver receives the second set of syndromes and produces an indication of zero or more error locations and an indication of zero or more error values.

Abstract: A sequential element having a master stage and a slave stage and a method of testing an IC having a scan chain and an IC. In one embodiment, the sequential element includes an input scan multiplexor configured to place the sequential element in a functional mode or a scan mode in response to a scan enable input and a scan out driver coupled to the slave stage and configured to provide a scan out signal when the sequential element is in the scan mode, the scan out driver coupled to an inverted scan enable input for a negative voltage supply.

Abstract: A method for synchronizing data operations in a multi-threaded computer system using a hybrid lock data structure that allows the computer system to dynamically implement a low contention cost lock or a low overhead cost lock based on the intensity of the memory operation.

Abstract: A method of manufacturing a through-substrate-via structure. The method comprises providing a substrate having a front-side and an opposite back-side. A through-substrate via opening is formed in the front-side of the substrate. The through-substrate-via opening does not penetrate an outer surface of the back-side of the substrate. The through-substrate-via opening is filled with a solid fill material. Portions of the substrate from the outer surface of the back-side of the substrate are removed to thereby expose the fill material. At least portions of the exposed fill material are removed to form a back-side through-substrate via opening that traverses an entire thickness of the substrate. The back-side through-substrate via opening is filled with an electrically conductive material.

Abstract: Disclosed is an external connector for a solid insulated load break switchgear. A semi-conductive layer for uniformly distributing an inner field is formed in a body part of a connector to uniformly distribute an inner field. This may prevent partial lowering of an insulating performance of the connector to enhance the insulating performance of the connector. Furthermore, a semi-conductive layer for uniformly distributing an outer field is formed between the connector and a bushing coupled to an upper end of the connector, and between the connector and a plug coupled to a lower end of the connector. This may allow an electric field to be uniformly distributed to a part connected to a ground surface of an arc extinguishing part.

Abstract: In one embodiment, a music detection (MD) module accumulates sets of one or more frames and performs FFT processing on each set to recover a set of coefficients, each corresponding to a different frequency k. For each frame, the module identifies candidate musical tones by searching for peak values in the set of coefficients. If a coefficient corresponds to a peak, then a variable TONE[k] corresponding to the coefficient is set equal to one. Otherwise, the variable is set equal to zero. For each variable TONE[k] having a value of one, a corresponding accumulator A[k] is increased. Candidate musical tones that are short in duration are filtered out by comparing each accumulator A[k] to a minimum duration threshold. A determination is made as to whether or not music is present based on a number of candidate musical tones and a sum of candidate musical tone durations using a state machine.

Abstract: A method of manufacturing an IC, comprising providing a substrate having a first side and a second opposite side, forming a STI opening in the first side of the substrate and forming a partial TSV opening in the first side of the substrate and extending the partial TSV opening. The extended partial TSV opening is deeper into the substrate than the STI opening. The method also comprises filling the STI opening with a first solid material and filling the extended partial TSV opening with a second solid material. Neither the STI opening, the partial TSV opening, nor the extended partial TSV opening penetrate an outer surface of the second side of the substrate. At least either: the STI opening and the partial TSV opening are formed simultaneously, or, the STI opening and the extended partial TSV opening are filled simultaneously.

Abstract: In one embodiment, a pause-based music detection (MD) module detects music by analyzing pauses in a received audio signal. The energy of each frame of the signal is compared to an energy threshold to determine whether the frame corresponds to background noise only (i.e., a pause) or sound such as speech or music. A window having a number of frames is analyzed to determine whether there is a pause within the window. If no pauses are detected in the window, then the current frame is presumed to correspond to music. If a pause is detected, then the current frame is presumed to correspond to speech. In another embodiment, the pause-based MD module output is applied to Boolean “OR” logic along with a tone-based MD module output to generate a final MD decision. The tone-based MD module detects music by analyzing tones in the signal using any suitable tone-based MD algorithm.

Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.

Abstract: A method of compressed picture reconstruction using a plurality of post-processed reference pictures. The method generally includes the steps of (A) generating a first of a plurality of reconstructed pictures by decoding a first of a plurality of compressed pictures using at least one of a plurality of non-post-processed reference pictures buffered in a reference memory, wherein the compressed pictures are received in an input bitstream, (B) generating a first of a plurality of processed pictures by artifact processing the first reconstructed picture to remove artifacts, (C) buffering in the reference memory both (i) the first reconstructed picture as one of the non-post-processed reference pictures and (ii) the first processed picture as one of the post-processed reference pictures and (D) generating a second of the reconstructed pictures by decoding a second of the compressed pictures using at least one of the post-processed reference pictures buffered in the reference memory.

Abstract: A method for transitioning a video system is disclosed. The method generally includes a first step for (A) executing in a processing circuit a standby code stored in a nonvolatile memory while the video system is in an off state, the off state defining a low power configuration for the processing circuit and a power off condition for the video system, the standby code being responsive to a plurality of wake up conditions to wake up the video system. In a second step, the method may (B) store an application code in a volatile memory while in the off state, the application code configured to operate the video system while in an on state of the video system. The method generally includes a third step for (C) transitioning from the off state to the on state upon detection of at least one of the wake up conditions. A step for (D) executing in the processing circuit the application code while in the on state to decode video may also exist in the method.

Abstract: In exemplary embodiments, a skewed interleaving function for iterative code systems is described. The skewed interleaving function provides a skewed row and column memory partition and a layered structure for re-arranging data samples read from, for example, a first channel detector. An iterative decoder, such as an iterative decoder based on a low-density parity-check code (LDPC), might employ an element to de-skew the data from the interleaved memory partition before performing iterative decoding of the data, and then re-skew the information before passing decoded samples to the de-interleaver. The de-interleaver re-arranges the iterative decoded data samples in accordance with an inverse of the interleaver function before passing the decoded data samples to, for example, a second channel detector.

Abstract: A method and disk drive for calibrating a phase of a clock in the disk drive. The phase of the clock in the disk drive is changed such that a rate of change for the phase is substantially constant. A pattern of data is written to a magnetic material in the disk drive after the rate of change for the phase becomes substantially constant and while changing the phase of the clock. A selected phase of the clock at which the pattern of data that is written on the magnetic material has a desired quality is identified using the rate of change for the phase, a first point in time at which a timing mark on the magnetic material is read, a second point in time at which the timing mark is read, and a third point in time at which the pattern of data has the desired quality.