Abstract: A method is provided for performing caching in a processing system including at least one data cache. The method includes the steps of: determining whether each of at least a subset of cache entries stored in the data cache comprises data that has been loaded using fetch ahead (FA); associating an identifier with each cache entry in the subset of cache entries, the identifier indicating whether the cache entry comprises data that has been loaded using FA; and implementing a cache replacement policy for controlling replacement of at least a given cache entry in the data cache with a new cache entry as a function of the identifier associated with the given cache entry.

Abstract: A method is provided for performing cache line fetching and/or cache fetch ahead in a processing system including at least one processor core and at least one data cache operatively coupled with the processor. The method includes the steps of: retrieving post modification information from the processor core and a memory address corresponding thereto; and the processing system performing, as a function of the post modification information and the memory address retrieved from the processor core, cache line fetching and/or cache fetch ahead control in the processing system.

Abstract: Methods and apparatus are provided for gain estimation using servo data with improved bias correction. The gain is estimated using a preamble in a servo sector by obtaining a first gain estimate using a first gain estimation algorithm (such as a Zero Gain Start Algorithm) and a first portion of the preamble; storing the first portion of the preamble in a memory buffer; obtaining a second gain estimate using a second gain estimation algorithm (such as a Zero Forcing algorithm) and the first portion of the preamble; and processing Servo Address Mark (SAM) and Gray data in the servo sector using the first gain estimate substantially simultaneous to the step of obtaining the second gain estimate. A gain error can be obtained by calculating a difference between the first gain estimate and the second gain estimate. The gain error can be used in burst processing of the servo data.

Abstract: Described embodiments provide for transferring data between a host device and a storage media. A host data transfer request is received and a total size of the data transfer is determined. One or more contexts corresponding to the total size of the requested transfer are generated and are associated with transfers of data. If the data transfer is a write operation, one or more data segments from the host device are transferred into a buffer. The combined size of the data segments corresponds to the total size of the data transfer. In accordance with the contexts, the one or more data segments are transferred from the buffer to the storage media. If the requested data transfer is a read operation, in accordance with the contexts, data from the storage media is retrieved into a buffer and grouped into one or more segments, which are transmitted to the host device.

Abstract: An apparatus having a memory and a controller is disclosed. The memory may be configured to (i) store a plurality of cache lines, each of the cache line comprising a plurality of locations including a respective end location and (ii) accessing a particular one of the cache lines identified by a cache address signal. The controller may be configured to (i) buffer a plurality of line pointers, each of the line pointers identifying a respective boundary one of the locations in one of the cache lines and (ii) generate the cache address signal in response to a processor address signal hitting a given one of the locations residing between the respective boundary location and the respective end location.

Abstract: The present invention is directed to a method for deterministic Serial Attached Small Computer System Interface (SAS) discovery and configuration. The method includes transmitting a Serial Management Protocol (SMP) DISCOVER Request from a node of a SAS domain to each expander of the SAS domain. The method further includes receiving SMP DISCOVER Responses at the node from each expander of the SAS domain. The method further includes comparing BROADCAST (CHANGE) RECEIVED (BCR) counts provided in each of the received SMP DISCOVER Responses to stored BCR counts, said stored BCR counts having been recorded and stored by the node prior to said transmitting of said SMP DISCOVER Request. The method further includes updating the stored BCR counts based upon said received BCR counts. The method further includes selectively transmitting a second SMP DISCOVER Request from the node to at least one, but not all of the expanders of the SAS domain.

Abstract: The present invention is a device for detecting short burst errors. The device includes a first signal input, wherein the first signal input is configured to receive a first signal. The device includes a second signal input, wherein the second signal input is configured to receive a second signal. The device includes a logic gate, wherein the logic gate is operable for receiving the first signal vial the first signal input, receiving the second signal via the second signal input, and generating a logic output gate signal based on the received first signal and the second signal. Furthermore, the device includes a filter, wherein the filter is configured for receiving the logic output gate signal from the logic gate and generates a filter output signal based upon the received logic output gate signal, wherein the filter output signal is operable for flagging errors.

Abstract: A network node, such as an Ethernet switch, is configured to monitor packet traffic using regular expressions corresponding to Access Control List (ACL) rules. In one embodiment, the regular expressions are expressed in the form of a state machine. In one embodiment, as packets are passed through the network node, an access control module accesses the packets and traverses the state machine according to certain qualification content of the packets in order to determine if respective packets should be permitted to pass through the network switch.

Abstract: The present invention is a method for drive management and data placement in an archival storage system having a set of drives. The method includes mapping redundant data stripes onto the drives. A first active data stripe, located on a first subset of the drives, is then selected from the mapped data stripes. The first subset is placed into a normal power state and a second subset of the drives is placed into a low power state. Data is then written to the first active data stripe. Before the first active data stripe is fully used, the method includes selecting a next active/second active data stripe from the mapped data stripes, the second active data stripe being at least partially located on the second subset. The method may be performed by a system which implements MAID techniques for drive management and CRUSH for data placement.

Abstract: A method includes executing, in each of a number of nodes of a cluster communication system, a specialized instance of an operating system privileged to control a corresponding hypervisor configured to consolidate one or more VM(s) on a system hardware. The one or more VM(s) is configured to be associated with a non-privileged operating system. The method also includes providing a cluster stack associated with the specialized instance of the operating system on the each of the number of nodes to enable communication between peers thereof in different nodes, and controlling the one or more VM(s) as a cluster resource through the cluster stack.

Abstract: A SAS expander collects data access information associated with a nexus and determines whether a data prefetch is appropriate. The SAS expander identifies potential data blocks utilizing previous data requests of the nexus. The SAS expander issues a data request to the target for the potential data blocks. The SAS expander stores the potential data blocks within a prefetch cache for future utilization within a data read.

Abstract: A lighting device having a support module comprising a disk for supporting LEDs and having an outer perimeter with a curved portion and a housing with an inner surface having a curved portion configured to receive the curved portion of the support module disk so that the disk can be aimed by external adjustment devices with the curved portions of the disk and housing remaining in contact. The external adjustment device facilitates aiming of the disk without the need to open the sealed LED module. Heat from the LEDs and/or LED mounting assembly can be transferred via the contact of the curved surfaces to the outside air while the module is tilted, e.g., up to 15 degrees, or more, from vertical.

Abstract: Methods and structure for improved migration of a logical volume storage migration using storage array managed server agents. Features and aspects hereof provide for a storage array (e.g., a RAID or other storage controller in a storage array) to manage the migration of a logical volume from a first physical storage volume to a second physical storage volume. The storage array cooperates with a server agent in each server configured to utilize the logical volume. The server agent provides a level of “virtualization” to map the logical volume to corresponding physical storage locations of a physical storage volume. The storage array exchanges information with the server agents such that the migration is performed by the storage array. Upon completion of the migration, the storage array notifies the server agents to modify their mapping information to remap the logical volume to a new physical storage volume.

Abstract: Decision modules are strategically located along with various modules to route signals from either a test pattern generator or the data link layer through the various modules for performing scrambling, encoding, and serializing procedures on the signals before transmission of the signals on a serial bus. Decision modules are strategically placed along with various modules to route signals to either a test pattern checker or the data link layer through the various modules for performing descrambling, decoding, and deserializing procedures on the signals after receiving the signals from a serial bus.

Abstract: A method includes addressing, through a command generated by an application executing on a computing platform, one or more device(s) in storage communication with the computing platform based on an appropriate communication link. The method also includes accessing, based on the addressing, a physical register of the one or more device(s) through an appropriate interface therein. Further, the method includes obtaining statistical information associated with a performance of the one or more device(s) at the computing platform through the access of the physical register.

Abstract: A method for selectively storing data identified by a software application in higher performance media may include executing control programming for an operating system and a software application hosted by the operating system. The software application assigns a first importance level to a first portion of data and a second importance level to a second portion of data. A first portion of data having the first importance level assigned by the software application is stored in a first storage medium at the instruction of the operating system. A second portion of data having the second importance level assigned by the software application is stored in a second storage medium at the instruction of the operating system. The second storage medium has at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: In described embodiments, a data communication device employing, for example, a modem and a data access arrangement (DAA) electrically connected to a telephone network has an increased surge immunity through use of improved hook switch driver and line modulation driver circuitry. In accordance with described embodiments, hook switch driver circuitry exhibits decreased surge power dissipation by maintaining the hook switch driver transistors in saturation at higher currents while reducing the collector-emitter voltage across hook switch driver transistors, and line modulation driver circuitry exhibits decreased total surge power dissipation by i) limiting surge voltage ii) over voltage stress of the line driver transistor.

Abstract: Various embodiments of the present invention provide systems and methods for analog to digital conversion. As an example, a circuit for converting analog signals to digital signals is disclosed. The circuit includes a variable gain amplifier circuit, an analog to digital converter circuit, and a summation circuit. The variable gain amplifier circuit is operable to apply a first gain value to an input to yield a first amplified output, and to apply a second gain value to the input to yield a second amplified output. The analog to digital converter circuit is operable to receive a derivative of the first amplified output and to provide a corresponding first digital sample, and to receive a derivative of the second amplified output and to provide a corresponding second digital sample. The summation circuit is operable to combine the first digital sample and the second digital sample.

Abstract: A storage medium recording a cell library having one or more cells that may be readable by a computer and may be used by the computer to design an integrated circuit. The one or more cells may have a physical dimension parameter and a channel width parameter. The physical dimension parameter may be a footprint of the one or more cells. The channel width parameter may have a minimum driver size and a maximum driver size. The channel width parameter may define a range within which a tool varies the channel width between the maximum driver size and the minimum driver size during a design flow of the integrated circuit based upon one or more power criteria without changing the footprint.

Abstract: An apparatus comprising a write circuit, a processing circuit and a monitor circuit. The write circuit may be configured to generate one or more write control signals in response to an input signal. The processing circuit may be configured to generate an intermediate control signal in response to (i) the input signal, (ii) a reference clock signal and (iii) one or more user input signals. The monitor circuit may be configured to generate a sample signal in response to (i) the write control signals and (ii) the intermediate signal. The sample signal may represent a waveshape of the write control signals used to monitor writing to a data storage system.