Abstract: An improved integrated circuit cell architecture is provided for configurability between a memory cell or logic elements. The cell architecture is configured on variable layers above a first layer of metal, with the first layer of metal and layers therebelow reserved as fixed layers. By coupling a maximum of two layout cells together, a single-port or dual-port memory cell is realized. Likewise, by interconnecting transistors within a single cell or transistors among two or more cells, a logic device is realized. Within each cell, the bit lines are arranged on a layer separate from the wordlines, and extend orthogonal to each other.

Abstract: A method of configurable decoding is disclosed. The method generally includes the steps of (A) receiving a variable value in a configuration signal, (B) calculating a plurality of first syndromes corresponding to a particular codeword of a plurality of codewords received in an input signal, the particular codeword having a plurality of information symbols and a plurality of parity symbols coded such that up to a fixed value of a plurality of errors in the particular codeword are correctable, the fixed value being greater than the variable value, (C) transforming the first syndromes into a plurality of second syndromes such that no greater than the variable value of the errors in the particular codeword are correctable and (D) generating an intermediate signal carrying the second syndromes.

Abstract: A system, apparatus and method for generating extracted timing model files, such as macro library files, are disclosed. A user interface or data template is provided to an engineer that allows for the population of data within particular fields related to timing characteristics of an IP block, cell or core. Various types of data and fields may be provided into the user interface or data template. The location of relevant files, such as a cell or core netlist, may be provided within the template. Additionally, one or more modes may be selected by the user to define the manner in which the ETM file(s) are to be generated. An ETM file is automatically generated using the information provided in the data template.

Abstract: Methods and systems for encoding and/or decoding digital signals representing serial attached SCSI (SAS) out of band (OOB) signals exchanged over an optical communication between two SAS devices. A SAS OOB signal to be transmitted from a first SAS device to a second SAS device is first encoded as a digitally encoded signal representing the analog SAS OOB signal and then transmitted over an optical communication medium to another SAS device. A receiving SAS device coupled to an optical communication medium decodes a received digitally encoded signal to detect a received, encoded SAS OOB signal and processes the received SAS OOB signal when receipt is detected. The digitally encoded signal may comprise an idle word portion and a burst word portion to represent various SAS OOB signals. Further, the digitally encoded signal may be precomputed in a variety of disparity forms and stored in a memory for lookup and retrieval.

Abstract: Techniques are disclosed for in-band communication of alarm status information or other information between physical layer devices comprising a working device and a protection device in a network-based communication system. In one aspect, a protection receive signal is monitored in the protection device for the presence of alarm status information. The protection device encodes alarm status information extracted from the protection receive signal, and inserts the encoded alarm status information into one or more designated portions of a protection loop-back signal supplied from the protection device to the working device. The protection loop-back signal is monitored in the working device and the encoded alarm status information therein is decoded and utilized by the working device to initiate a protection switching operation.

Abstract: Methods and apparatus for increasing the accuracy of timing characterization of a circuit including one or more cells in a cell library are provided. One method includes the steps of: performing cell library timing characterization for each of the cells in the circuit for at least first and second prescribed temperatures, the first and second temperatures corresponding to first and second PVT corners, respectively, in the cell library; calculating respective cell delays for the one or more cells in the circuit, the cell delay calculation being a function of temperature for each instance of the one or more cells; and incorporating the cell delay calculation into the timing characterization for each of the cells in the circuit to thereby increase the accuracy of the timing characterization.

Abstract: Methods and systems for simplified error recovery in a SAS device. A SAS device (e.g., a SAS/SSP target device such as a storage device) enhanced in accordance with features and aspects hereof NAKs a received frame that has an error and then NAKS all subsequently received frames, regardless of whether received with or without error, until the connection is closed. The second SAS device (e.g., a SAS/SSP initiator) then performs required error recovery by re-establishing a connection and re-transmitting all previously NAKed frames. The enhanced SAS thereby simplifies logic for error recovery.

Abstract: Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage.

Abstract: A lighting apparatus having a base member and a directional member are shown and described. The base member includes a first surface having a plurality of reflective elements extending therefrom. The base member also including a plurality of openings arranged in a pattern. Each openings is configured to receive a respective light source. The directional member has a portion of a reflective surface positioned relative to at least one opening to reflect light radiating from a lighting source disposed within the opening towards a portion of at least one of the reflective elements extending from the base member.

Abstract: Embodiments of the invention include a device and method for improved battery learn cycles for battery backup units within data storage devices. The backup unit includes a first battery pack, a corresponding charge capacity gauge, one or more second battery packs, a corresponding charge capacity gauge, and a controller switch configured to select only one battery pack for a learn cycle at any given time. The charge capacity gauges are such that, at the end of the learn cycle discharge phase, the depth of discharge of the learn cycle battery pack is such that the charge capacity of the learn cycle battery pack combined with the full charge capacity of the remaining battery packs is sufficient for the device cached data to be off-loaded to a physical data storage device, and the data storage device does not have to switch from a write-back cache mode to a write-through cache mode.

Abstract: An apparatus comprising a logically contiguous group of at least two drives, a loop and a compression/decompression circuit. Each of the drives comprises (i) a first region configured to store compressed data of a previous drive and (ii) a second region configured to store uncompressed data of the drive. The loop may be connected to the next drive in the logically contiguous group. The compression/decompression circuit may be configured to compress and decompress the data stored on each of the drives.

Abstract: In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.

Abstract: A method includes segmenting a virtual volume into an active area configured to map to a first type of storage and a non-active area configured to map to a second type of storage through a storage virtualization engine. The second type of storage includes data associated with a host device and the first type of storage includes point-in-time images corresponding to the data associated with the host device. The first type of storage offers a higher performance than that of the second type of storage. The method also includes allocating a portion of space in the first type of storage to serve as a cache memory during a write operation and/or a read operation, and reducing a latency associated with the response to a write request and/or a read request through performing the corresponding write operation and/or the read operation through the first type of storage.

Abstract: A method and apparatus for synchronizing input/output commands is provided. An incoming command mask representing an incoming input/output command associated with a memory region is created. In response to a determination that a pending input/output command associated with the memory region is pending, a bitwise inversion operation is performed on the incoming command mask to form a modified incoming command mask. A bitwise AND operation is performed on the modified incoming command mask and the pending command mask to form a pending command locking mask associated with the pending input/output command. A bitwise OR operation is performed between an existing memory lock for a same type of commands and incoming command bit mask to form a new memory region lock.

Abstract: A method for caching data in a storage medium implementing tiered data structures may include storing a first portion of critical data at the instruction of a storage control module. The first portion of critical data may be separated into data having different priority levels based upon at least one data utilization characteristic associated with a file system implemented by the storage control module. The method may also include storing a second portion of data at the instruction of the storage control module. The second storage medium may have at least one performance, reliability, or security characteristic different from the first storage medium.

Abstract: A method and controller device for upgrading the firmware in a virtualized storage environment having a first storage controller and a second storage controller, wherein each storage controller includes a first virtual machine, at least one second virtual machine and a storage device. The method includes upgrading the current firmware of the first virtual machine in the first storage controller to a new firmware version, upgrading the current firmware of the second virtual machine in the first storage controller to a new firmware version, upgrading the current firmware of the first virtual machine in the second storage controller, upgrading the current firmware of the second virtual machine in the second storage controller, and rolling back the firmware version of all virtual machines in the first and second storage controllers if the firmware upgrade of any of the virtual machines in the first and second storage controllers is not successful.

Abstract: In one embodiment, a multistage interconnection network (MIN) has two or more configurable stages, each stage having a plurality of switches. The network has one or more unused input terminals, each mapped using fixed switch connections to an unused output terminal. The network also has a set of used input terminals that are selectively mapped to a set of used output terminals based on values of control signals supplied to the stages. Each stage receives a different control signal, and each control signal is generated by cyclically shifting a control seed by a corresponding cyclic-shift value. Fixing the mappings of the unused terminals ensures that the used input terminals are not mapped to any unused output terminals. By storing only the control seed, memory requirements are reduced over networks that explicitly store individual control signals for all of the stages.

Abstract: Methods and structure for reprogramming firmware in a storage controller using a virtual machine management (VMM) environment. A storage process (current firmware) in the storage controller operates in a current virtual machine (VM) under control of a hypervisor. Reprogrammed (new) firmware is loaded into a new virtual machine under control of the hypervisor. The new firmware initializes and directs the current firmware to quiesce its processing. The new firmware also requests the hypervisor to map data in the memory space of the current virtual machine into the memory space of the new virtual machine and to transfer ownership/control of devices and network addresses from the current virtual machine to the new virtual machine. The new firmware operating on the new virtual machine then takes control of the storage controller and resumes processing of requests.

Abstract: A method of forming an electronic device bond pad includes providing an electronic device substrate having an Al bond pad located thereover. An aluminum layer is formed over the Al bond pad. A metal layer is formed located between the Al bond pad and the aluminum layer. The metal layer comprises one or more of Ni, Pd and Pt and has a total concentration of Ni, Pd and/or Pt of at least about 50 wt. %. A gold bond wire may be attached to the aluminum layer.