Abstract: A storage area network system having a data storage means for storing computer data, a storage manager routine running on a client, the storage manager routine having functional elements for directing snapshots to be taken of the computer data on the data storage means, and a snapshot ranking manager for determining characteristics of the snapshots, and for selectively deleting given ones of the snapshots based at least in part on the characteristics of the snapshots. The characteristics of the snapshots might include the type of application that uses the data in the logical volume from which the snapshots were taken, or mission critical aspects of the data.

Abstract: An apparatus for monitoring of received information in a communication device comprises a first buffer having a plurality of storage elements adapted to store respective portions of the received information, a second buffer coupled to the first buffer and having a plurality of storage elements corresponding to respective ones of the storage elements of the first buffer, and controller circuitry coupled to the buffers and operative to detect a message sequence comprising a plurality of the portions of the received information. The second buffer stores a previously-detected message sequence loaded from the first buffer into the second buffer under control of the controller circuitry. The controller circuitry in detecting a current message sequence is configurable in at least first and second different monitoring modes each associated with a different message format. The monitoring mode of the controller circuitry may be adaptively configured based at least in part on a detected message sequence.

Abstract: An apparatus including one or more reader circuits, one or more writer circuits, and a loopback channel. The one or more reader circuits may be configured to read data from a magnetic medium. The one or more writer circuits may be configured to write data to the magnetic medium. The loopback channel is coupled between the one or more reader circuits and the one or more writer circuits.

Abstract: A method for discarding perpetually-rejected packets in a fabric-based interconnect having a reliable physical layer is disclosed. A transmitting component keeps a count of the number of negative acknowledgements (NAKs) it receives from the receiving component for packets the transmitting component sends. If the transmitting component receives a number of consecutive NAKs for the same packet that exceeds some pre-determined threshold, the packet is not resent, but is, instead, treated as having been acknowledged, and subsequent packets are allowed to be transmitted. Higher-level processes are then notified of the problem so as to allow the error to be dealt with at a higher level, but without obstructing the flow of packets on the physical layer.

Abstract: Techniques are taught for reducing writes, and estimating and displaying estimated remaining lifetime of non-volatile memories. The write reducing is optionally via determining a difference between write operation results and data stored in the non-volatile memories. The estimated remaining lifetime is optionally based at least in part on a previous lifetime. The displaying is optionally via a gauge.

Abstract: Methods and structure for on-chip self-test of clock jitter for an application clock signal generated within an integrated circuit (IC). Features and aspects hereof provide for acquisition of samples of an application clock signal within the IC and counting the number of samples having a predetermined value. The count is compared to acceptable limits range values to generate a pass/fail signal of the IC use by external automated. A sample clock is generated based on the reference clock used by a Phase Locked Loop (PLL) circuit. An incremental delay is added to the sample clock pulse such that the sequence of samples “walk” through an application clock pulse waveform to sense clock jitter at various points of the waveform based on the counts. Acceptable limits range for the count at each sampled point, the incremental delay, and the number of samples at each delayed value may be user programmed.

Abstract: A method for virtual function boot in a system including a single-root I/O virtualization (SR-IOV) enabled server includes loading a PF driver of the PF of a storage adapter onto the server utilizing the virtual machine manager of the server; creating a plurality of virtual functions utilizing the PF driver, detecting each of the virtual functions on an interconnection bus, maintaining a boot list associated with the plurality of virtual functions, querying the storage adapter for the boot list utilizing a VMBIOS associated with the plurality of VMs, presenting the detected boot list to a VM boot manager of the VMM, and booting each of the plurality of virtual machines utilizing each of the virtual functions, wherein each VF of the plurality of VFs is assigned to a VM of the plurality of VMs via an interconnect passthrough between the VMM and the plurality of VMs.

Abstract: A method, an apparatus and/or a system of serial attached small computer system interface (SAS) domain access through a universal serial bus (USB) interface of a data processing device. A method includes communicatively coupling a serial attached small computer system interface (SAS) domain to the data processing device through the universal serial bus (USB) interface of the data processing device via an expander device. The method also includes accessing a SAS device of the SAS domain and/or the SAS domain through the USB interface of the data processing device via the expander device. The method further includes bridging through a firmware of the expander device between a USB command of the data processing device and a SAS command of the SAS domain to communicate between the data processing device and the SAS domain.

Abstract: Methods and systems for using one or more solid-state drives (SSDs) as a shared cache memory for a plurality of storage controllers coupled with the SSDs and coupled with a plurality of storage devices through a common switched fabric communication medium. All controllers share access to the SSDs through the switched fabric and thus can assume control for a failed controller by, in part, accessing cached data of the failed controller in the shared SSDs.

Abstract: A storage array is disclosed. The storage array may comprise a plurality of storage units configured for providing data storage; a processing module configured for hosting a virtual machine; and an application integration framework provided by the virtual machine. The application integration framework may comprise an application interface configured for interfacing with at least one application running on an application server, where the application server is communicatively connected with the storage array. The application integration framework may further comprise a software development kit (SDK) communicatively coupled to the application interface via a communication module, the SDK being configured for providing a programmatic interface to the at least one application and enabling the at least one application for delegating at least a portion of data processing operations to the storage array.

Abstract: In one embodiment, a configurable communications system accommodates a plurality of different transmission word sizes. In a transmit path, the system inserts a number of padding bits corresponding to missing user-data bits onto the end of an input data sequence to generate a set of data having N bits. The N bits are interleaved and error-correction (EC) encoded to generate parity bits corresponding to an EC codeword. The parity bits are de-interleaved and multiplexed with the input data stream to generate a transmission word. In a receive path, a channel detector recovers channel values corresponding to the transmission word. Padding values, corresponding to the missing-bit locations, are inserted among the channel values. The resulting channel values are interleaved and EC decoded to recover the EC codeword. The data bits of the codeword are de-interleaved, and the padding bits corresponding to the missing channel values are discarded.

Abstract: Described embodiments provide skip operations for transferring data to or from a plurality of non-contiguous sectors of a solid-state memory. A host layer module sends data to, and receives commands from, a communication link. Received commands are one of read requests or write requests, with commands including i) a starting sector address, ii) a skip mask indicating the span of all sector addresses in the request and the sectors to be transferred, iii) a total number of sectors to be transferred; and, for write requests, iv) the data to be written to the sectors. A buffer stores data for transfer to or from the solid-state memory. A buffer layer module i) manages the buffer, ii) segments the span of the request into a plurality of chunks, and iii) determines, based on the skip mask, a number of chunks to be transferred to or from the solid-state memory.

Abstract: Disclosed is a method of improving a synthesized circuit design comprising searching the synthesized circuit design for a first instance of a first pattern of gates. The first instance is removed from the synthesized circuit design. The first instance is replaced with a non-synthesized cell. A method of altering a multiplexer implementation comprises receiving a netlist that describes a synthesized logic circuit design. Parsing the netlist to detect a first instance of a first pattern of gates that implements a first multiplexer. The first instance is replaced in the netlist with a technology implementation of the first multiplexer.

Abstract: A method of designing a logic circuit based on one of the functions of the form fn=x1 (x2 & (x3 (x4 & . . . xn . . . ))) and f?n=x1 & (x2 (x3 & (x4 . . . xn . . . ))), by (a) selecting n as the number of variables of the logic circuit, (b) testing n against a threshold, (c) for values of n less than the threshold, using a first algorithm to design the logic circuit, (d) for values of n greater than the threshold, using a second algorithm to design the logic circuit.

Abstract: Described embodiments provide a method of recovering storage space on a solid state disk (SSD). An index and valid page count are determined for each block of a segment of an SSD. If the valid page count of at least one block in the segment is zero, a quick clean is performed. A quick clean deallocates blocks having zero valid pages and places them in a queue for erasure. Otherwise, a deep clean is performed. A deep clean determines a compaction ratio, N-M, wherein N is a number of partially valid blocks and M is a number of free blocks required to compact the valid data from the N partially valid blocks into M entirely valid blocks. At least one data structure of the SSD is modified to refer to the M entirely valid blocks, and the N partially valid blocks are placed in the queue for erasure.

Abstract: A storage array controller may include a virtual machine manager for managing a storage array application virtual machine and a dedicated multiplexer virtual machine. The storage array application virtual machine and the dedicated multiplexer virtual machine may be communicatively coupled via a plurality of virtual machine manager coupling drivers. The storage array controller may also include a dedicated inter controller link for communicatively coupling the storage array controller with a second storage array controller. The dedicated multiplexer virtual machine may be configured for coupling with a second dedicated multiplexer virtual machine included with the second storage array controller via a device driver communicating across the dedicated inter controller link.

Abstract: A basic cell circuit architecture having plurality of cells with fixed transistors configurable for the formation of logic devices and/or single/dual port memory devices within a structured ASIC is provided. Different configurations of ensuing integrated circuits are achieved by forming variable interconnect layers above the fixed structures. The circuit architecture can achieve interconnection of transistors within a single cell and/or across multiple cells. The interconnection can be configured to form basic logic gates as well as more complex digital and analog subsystems. In addition, each cell contains a layout of transistors that can be variably coupled to achieve a memory device, such as a SRAM device. By having the capability of forming either a logic circuit element, a memory device, or both, the circuit architecture is both memory-centric and logic-centric, and more fully adaptable to modern-day SoCs.

Abstract: A circuit for stabilizing soft bits in a bit stream, the circuit having a first register to receive an initial read of the bit stream, a second register to receive a subsequent read of the bit stream, a comparator to compare the initial read of the bit stream to the subsequent read of the bit stream, a third register to receive a comparison string having bits set in positions where the initial read of the bit stream and the subsequent read of the bit stream do not match, indicating a soft bit in the positions, and an accumulator to receive the comparison string for multiple subsequent reads of the bit stream, and track positions of all soft bits detected during the multiple subsequent reads.

Abstract: A method of designing an integrated circuit and a model of an integrated circuit block, an electronic design automation tool, an apparatus and a computer-readable medium are disclosed herein. In one embodiment, the method of designing an integrated circuit includes: (1) generating a timing budget for the integrated circuit employing designer input of the integrated circuit, (2) establishing design constraints for a block of the integrated circuit employing the timing budget, (3) creating an input and output timing budget for the block employing the design constraints, (4) combining implementation information for the integrated circuit based on designer knowledge with the input and output timing budget to generate an updated input and output timing budget and (5) generating a model of the block based on the updated input and output timing budget.

Abstract: Various embodiments of the present invention provide systems and methods for preparing and accessing super sector data sets. As an example, a data storage system including a storage medium is disclosed. The storage medium includes a first servo data region and a second servo data region separated by a user data region. The user data region includes at least a portion of a first codeword and a portion of a second codeword that are together associated with a common header data.