Abstract: Methods and systems for generating storage related load factor information for load balancing of multiple virtual machines operable in a cluster of multiple physical processors (such as a blade center). Load factor information is generated within a storage system relating to operation of the storage system as a whole and relating to each of multiple storage controllers in the storage system. The information so generated in the storage system is communicated to a load balancing element associated with the multiple virtual machines. The load balancing element then utilizes the storage related load factor information, optionally in combination with other load factor information, to distribute or redistribute the operation of the multiple virtual machines over the plurality of physical processors.

Abstract: A system and method for synchronizing and coordinating parallel, automated fault injection processes against storage area network arrays. In an exemplary embodiment, the stress test system includes a hierarchical lock file acting as a repository for lock and state data of storage area network resources. Further, such embodiment includes a plurality of knowledge sources communicatively coupled to the hierarchical lock file for monitoring activities of the storage area network resources and injecting faults. In addition, the system includes a controller for controlling access to the hierarchical lock file and coordinating activities of the plurality of knowledge sources. The plurality of knowledge sources are individual stress action words which are utilized by the hierarchical lock file to coordinate multiple, parallel stress tests against storage area network components without requiring modifications to the underlying code to be made.

Abstract: The present invention is a method and system for manufacturing an electronic device, such as a data storage device. The method includes generating a register including a desired device configuration. The register may include an identifier and radio signal information associated with the component so that the component may be tracked via a radio frequency identification device (RFID) physically associated with the component. Radio signals are monitored for signals associated with the component such as prior to inclusion into the electronic device to prevent improper assembly. An alert may be provided if a radio signal associated with a component included in the desired configuration is not present. The radio signals determined during monitoring are verified with the radio signals associated with the components included in the register. The components are assembled into the electronic device (or partially assembled device).

Abstract: During the design of semiconductor products which incorporates a user specification and an application set, the application set being a partially manufactured semiconductor platform and its resources, a template engine is disclosed which uses a simplified computer language having a character whereby data used in commands identified by the character need only be input once, either by a user or by files, and that data, after it has been verified to be correct, is automatically allocated to one or more templates used to generate shells for the specification of a final semiconductor product. Data must be correct and compatible with other data before it can be used within the template engine and the generated shells; indeed the template engine cooperates with a plurality of rules and directives to verify the correctness of the data.

Abstract: An apparatus and method are provided for powering an integrated circuit chip with a supply voltage generated externally to the chip. An on-chip clock signal is generated with a ring oscillator fabricated on the integrated circuit chip. The supply voltage is altered as a function of a difference between a frequency of the on-chip clock signal and a reference clock frequency.

Abstract: Various systems and methods for indicating the status of a communication are disclosed herein. For example, status indication methods are disclosed that include initiating a communication that allows for communication between two persons. Further, the methods include determining a combination of status. The combination of status is based on a determination of two or more of the following: a calendar status, a power status, an activity status, and a location status. A communication status message is updated based at least in part on the determined combination of status.

Abstract: System and Methods for Copying Digital Information from a Digital Media Various embodiments of the present invention provide systems and methods for copying or ripping digital information contained on one media to another media. In particular, some embodiments of the present invention provide methods and systems for copying digital information contained in a first fixed media onto another media by using digital information content corresponding to that maintained on the first fixed media, but obtained from a database.

Abstract: The present invention provides a system and method for designing and modularly expanding multiport bitcells. A modular design approach is described that reduces the complexity of designing multiport bitcells while complying with DFM rules across various semiconductor fabrication providers. The modular design may be parsed into modules such as read port modules, write port modules, and pull-up modules that may be easily interconnected to build a multiport bitcell. These modules may also be independently sized and assembled to achieve desired read margins, write margins, static noise margins as well as read access times and write times.

Abstract: A method for developing a circuit design is disclosed. The method generally includes the steps of (A) editing a file for a circuit design based on a plurality of edits received from a designer, the file containing a code written in a hardware description language, (B) characterizing the code in the file while the designer is editing the code to generate a plurality of characterization results and (C) generating a plurality of suggestions to the designer to modify the code based on a comparison of a plurality of goals for the circuit design and the characterization results.

Abstract: A multi-phase adaptive decision feedback equalizer minimizes post-cursor inter-symbol interference in a current data bit based on values of subsequent data bits in a data communication system. In one form, the receiver includes a plurality of modules each having a respective adaptive decision feedback equalizer. A processor responsive to output signals from each of the plurality of modules generates a plurality of coefficient values. The adaptive decision feedback equalizer has a plurality of taps receiving a respective output signal from one of the modules and a respective coefficient value to generate a respective correction signal. The correction signals are summed with the data signal and processed to recover the data. Pre-calculation of coefficients permits rapid selection of data. Multi-phase operation permits higher data frequencies.

Abstract: Methods and associated structures for utilizing write-back cache management modes for local cache memory of disk drives coupled to a storage controller while maintaining data integrity of the data transferred to the local cache memories of affected disk drives. In one aspect hereof, a state machine model of managing cache blocks in a storage controller cache memory maintains blocks in the storage controller's cache memory in a new state until verification is sensed that the blocks have been successfully stored on the persistent storage media of the affected disk drives. Responsive to failure or other reset of the disk drive, the written cache blocks may be re-written from the copy maintained in the cache memory of the storage controller. In another aspect, an alternate controller's cache memory may also be used to mirror the cache blocks from the primary storage controller's cache memory as additional data integrity assurance.

Abstract: An apparatus generally having a first memory and a circuit is disclosed. The first memory may be used for a motion estimation of a current block. The circuit may be configured to (i) determine if a search window for the current block is at least partially outside a boundary of a picture stored in a second memory, (ii) copy a first plurality of reference samples in the search window from the second memory to the first memory and (iii) map a plurality of reads from the first memory for a plurality of pad samples to the reference samples in the first memory, where the pad samples are determined to be outside the boundary.

Abstract: A semiconductor integrated circuit package incorporating a preformed one-piece mold cap and heatspreader assembly is disclosed. One implementation includes a substrate with a die attached to the substrate. The die is electrically connected with electrical connections formed on the substrate using bonding wires. A preformed one-piece integrated mold cap and heatspreader assembly attached to the substrate to enclose at least a portion of the bonding wires and the die. Methods of assembling semiconductor integrated circuit packages using a preformed one-piece integrated mold cap and heatspreader assembly are also disclosed.

Abstract: A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read logic IP block may be configured to communicate data from the double data rate (DDR) synchronous dynamic random access memory (SDRAM) to the memory controller. The master delay IP block may be configured to generate one or more delays for the read logic IP block. The address and control logic IP block may be configured to control the write logic IP block and the read logic IP block. The core is generally configured to couple the double data rate (DDR) synchronous dynamic random access memory (SDRAM) and the memory controller.

Abstract: A method for the binary zoning of a Storage Area Network (SAN) for security is disclosed, for a SAN with physical devices consisting of a first array of hosts (1) and a second array of storage devices (4), and a SAN Switch (2, 2A) coupled intermediate the hosts and the storage devices. The SAN Switch routes I/O commands and accepts zoning commands. The method is based on starting operation of the SAN with mutually isolated physical devices and accepting zoning commands only after running security verification procedures requiring that hosts be authenticated and that storage devices be identified. Zoning is dynamically controlled from a workstation (8) operated by a System Administrator entering meta-zoning instructions which are used to automatically program the zoning of the SAN Switch for legitimate physical devices. The method is implemented for security and booting of a SAN.

Abstract: A method of diverting void diffusion in an integrated circuit includes steps of forming an electrical conductor having a boundary in a first electrically conductive layer of an integrated circuit, forming a via inside the boundary of the electrical conductor in a dielectric layer between the first electrically conductive layer and a second electrically conductive layer of the integrated circuit, and forming a slot between the via and the boundary of the electrical conductor for diverting void diffusion in the electrical conductor away from the via.

Abstract: Methods and apparatus to enhance performance of Serial Advanced Technology Attachment (SATA) disk drives in Serial-Attached Small Computer System Interface (SAS) domains are described. In one embodiment, a data packets and/or commands communicated in accordance with SAS protocol may be converted into SATA protocol. Other embodiments are also described.

Abstract: An apparatus includes a first semiconductor die and at least one further semiconductor die. A substrate is attached to the first die and the further die and has an electrical interconnect pattern that interconnects contacts on the first die with respective contacts on the further die. Features of the interconnect pattern have positions on the substrate with smaller tolerances relative to positions of the contacts on the first die than to positions of the contacts on the further die.

Abstract: A scannable flip-flop and method are provided. The flip-flop includes a clock input, a normal data input, a test data input, a normal data output and a scan data output. The flip-flop has a normal operating mode during which the normal data output is enabled and the scan data output disabled and has a scan-shift mode during which the normal data output is disabled and the scan data output is enabled.

Abstract: A computer-aided circuit design application has a virtual node feature and a design tool. The virtual node feature is adapted to access design specification information in a first data format and to represent the accessed design specification information as a virtual data node object within a list of node objects in a second data format. The design tool is operable on the list of node objects and the virtual data node object.