Abstract: A method and system are provided for analyzing process window compliance of an integrated circuit design. Aspects of the present invention include identifying layout pattern configurations that have process windows that fail to meet respective local performance specifications; searching for any layout pattern configurations in a design that substantially match any of the identified layout pattern configurations; and modifying any matching layout pattern configurations found in the design to make the layout pattern configurations compliant with their respective process windows.

Abstract: A method for enhancing the performance of an IC package and media interface. Adding a fissure to a Flip-Chip type package improves the crosstalk performance of the package for both high and low frequencies. The wall of the fissure can be implemented with a heat spreader layer and can be connected to any AC ground such as VSS or VDD package planes. The fissures can also accommodate the ingress of an optical fiber, which allows for a direct interface with the transceivers. The direct optical fiber interface permits the removal of solder balls for high speed signal traces, with their respective vias. On-chip integrated LEDs or other similar light source transceivers can drive the high speed signal media. Selective deposition of low dielectric material can also improve the frequency response of high speed signal package traces.

Abstract: A method and apparatus are provided for protecting elements of a receiver from overvoltages in a pseudo-differential signal having a true signal and a reference voltage. The method and apparatus limit the true signal to a protection voltage, which is correlated to the reference voltage, to produce a protected true signal. The protected true signal and the reference voltage are applied to inputs of the receiver.

Abstract: Fabrication of electronic devices in the “metal layers” of semiconductor devices. Each metal layer includes a dielectric layer that supports a conductive layer, which includes electrically conductive pathways and electronic devices. The metal layers are stacked on top of each other such that the dielectric layers separate the adjacent conductive layers. The electronic devices may be passive devices such as resistors. The resistors are formed by depositing metal onto the dielectric layer and then implanting the metal with oxygen. The conductive layer may be formed of materials such as copper and aluminum.

Abstract: A method of isolating sources of variance in parametric data includes steps of: (a) cleaning a data set of measurements for a plurality of parameters; (b) generating a principal component analysis basis from the cleaned data set; (c) estimating an independent component analysis model from the principal component analysis basis; (d) calculating percentages of variance for the plurality of parameters explained by each component in the estimated independent component analysis model; (e) if the calculated percentages of variance indicate that a component is a minor component, then transferring control to step (f), else transferring control to step (g); (f) removing the minor component from the principal component analysis basis and transferring control to step (c); and (g) generating as output the estimated independent component analysis model wherein no component of the independent component analysis model is a minor component.

Abstract: The present invention provides a field programmable network application specific integrated circuit and a method of operation thereof. In one advantageous embodiment, the field programmable network application specific integrated circuit includes a media access controller and a programmable logic core having an array of dynamically configurable arithmetic logic units. The programmable logic core configured to interface with the media access controller and implement at least one application level function capable of generating meta-data. The media access controller and the programmable logic controller form at least a portion of a MP-block.

Abstract: An apparatus for motion estimation generally including a memory and a circuit. The circuit may be configured to (i) search for a first motion vector for a first current block among a plurality of first reference samples, (ii) copy a plurality of second reference samples from the memory and (iii) search for a second motion vector for a second current block among the second reference samples copied from the memory and at least a portion of the first reference samples.

Abstract: The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) and a spare delay cell is trained. A ratio is calculated for each Functional delay cell by dividing the Functional delay cells' setting into the spare delay cells' one-fourth cycle setting. These ratios reflect any process variation. Functional mode is then entered and a Master-Slave approach switched to, during which the spare delay cell repeats the training sequence continuously while the Functional delay cells delay the clocks from the RAM(Random Access Memory). Each Functional delay cell is updated at the end of each training sequence of the spare delay cell, compensating for voltage and temperature change, by dividing the ratio into the new spare delay cell one-fourth cycle setting.

Abstract: A device and method for retrofitting a light fixture from use with a lamp socket that employs an incandescent or metal halide lamp, to use with another lamp assembly. The lamp fixture has a collar with a base and an annular outer wall extending out from the base. The LED lamp device includes a neck base having an annular outer wall having a shaped outside surface that is placed into direct surface contact with the inner surface of the annular outer wall of the collar, to establish an effective heat-transferring interface. The shaped outer surface of the neck base provides proper fitting of the LED lamp device into the lighting fixture, and provides a heat-transferring interface over substantially all of the outer surface of the neck base, to dissipate heat away from the LED module. Aluminum material provides high thermal conductivity, light weight, availability, and low cost.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first composited data signal and a second composited signal in response to a first data signal having a first chroma format and a second data signal having a second chroma format. The second circuit may be configured to generate a first composited output signal having the first chroma format in response to the first and the second composited data signals.

Abstract: An application specific configurable logic IP module includes (1) a system level configuration controller; (2) at least one standardized interconnect communicatively coupled to the system level configuration controller; (3) at least one standardized configuration port for programming the application specific configurable logic IP module; (4) an embedded programmable logic fabric, communicatively coupled to the system level configuration controller and the at least one standardized interconnect, for mapping arithmetic functions into standard cells; (5) at least one scalable configurable logic module; and (6) a programmable routing matrix. The system level configuration controller is suitable for selecting a standard for the at least one standardized interconnect, the at least one standardized configuration port, and a number of embedded programmable logic functions, and for controlling the programmable routing matrix.

Abstract: The present invention is directed to a method of fabricating an integrated circuit package having decoupling capacitors using a package design conceived for use without decoupling capacitors. The package is implemented with a minimal redesign of the original design and not requiring any redesign of the signal trace pattern. The invention involves replacing top and bottom bond pads with via straps and then covering the top and bottom reference planes with a dielectric layer having conductive vias that electrically connect with the underlying via straps. Planes having the opposite polarity of the underlying reference plane are then formed on the dielectric layer. These planes include an array of bonding pads in registry with the vias. Decoupling capacitors are mounted to the top of the package and electrically connected with the plane on top of the package and the immediately underlying reference plane without the electrical connections to the capacitors passing through the signal planes of the package.

Abstract: A method of fabricating integrated circuits according to a first design. One first pattern is common with a second design, and one second pattern is unique to the first design. The first pattern is imaged using a first mask having first patterns formed in a block thereon. No other patterns of the first and second designs are formed on the first mask. The second patterns are imaged on the substrate using a second mask having second patterns formed in a block thereon. At least one third layer pattern is formed on the second mask.

Abstract: A reference circuit is described for creating a reference signal using a twin MONOS memory cell. A first portion of the twin MONOS memory cell connects to a charged and floating bit line a current source formed in a second portion of the twin MONOS cell that discharges the charged bit line to form a reference signal for a sense amplifier. The sense amplifier compares the reference signal to a signal from a selected memory cell upon which memory operations are being performed comprising read, erase verify and program verify.

Abstract: A self-standing reflector, and method of making same, comprising a main reflector formed from at least one sheet of reflective material, and at least one reflective insert joined to the main reflector. The main reflector is typically formed by folding a plurality of flat panels along fold lines pre-formed in the sheet into abutting relationship to define a predetermined three-dimensional reflector shape. The reflective insert can have a plurality of facets formed into its reflective surface and is joined to the interior surface of the folded main reflector, and has a reflecting surface disposed inboard from the interior reflective surface of the main reflector. The main reflector and the reflective inserts have a reflectance of at least 95% (Miro 4). The fold-up reflector with its reflective inserts directs reflected light to a predetermined area to provide improved area lighting with less light scatter and improved efficiency.

Abstract: A combination of an infrequently-called tiny multiplication unit and a “differential” unit that quickly computes T (n+1) basing on known T n. The schedule (how often the multiplication unit is called) can be considered as a parameter of the algorithm. The proposed architecture of the “differential” unit is efficient both in terms of speed (delay) and area (gate count).

Abstract: A test clocking scheme that separates the clock driving the functional logic and the memory from the clock driving the test logic and the memory. In other words, the test clocking scheme separates the memory functional clock from the memory test clock into two clock paths. The test clocking scheme provides for the ability to separately shut off either the memory functional clock source or the memory test clock source, provides that less power is required during production testing, and provides that simulation time is reduced during design verification because the functional logic is not clocked.

Abstract: A polishing pad having an upper layer with a first visual characteristic. The upper layer is adapted to erode against a pad conditioner at a uniform rate during a pad conditioning process. At least one lower layer with at least a second visual characteristic is disposed beneath the upper layer. The first visual characteristic is visually distinguishable from the second visual characteristic. The at least one lower layer is adapted to polish a substrate, where the visual distinguishability between the upper layer and the at least one lower layer provides a visual indication of whether the pad conditioning process has been accomplished in a uniform manner.

Abstract: A method for calibrating a data valid window including the steps of: (A) setting a base delay of one or more datapaths to a predetermined value, (B) determining an optimum offset delay value for each of the one or more datapaths based upon actual memory accesses and (C) delaying a read data strobe signal based upon the base delay and the optimum offset delay value for each of the one or more datapaths.