Abstract: A video decoder comprising (i) a post-processing filter block, (ii) a comfort noise addition block and (iii) a video value/range adjustment block, where the comfort noise addition block is integrated into a video output path of the video decoder. The post-processing filter block may be configured to perform one or more of noise reduction, spatial filtering and temporal filtering on luminance data. The comfort noise addition block may be configured to add comfort noise to the luminance data. The video value/range adjustment block may be configured to adjust one or both of a value and a range of the luminance data.

Abstract: A method of detecting potential failures from a corrected mask design for an integrated circuit includes steps of receiving as input a corrected mask design for an integrated circuit, searching the corrected mask design to find a critical edge of a polygon that is closer than a selected minimum distance from a polygon edge opposite the critical edge, constructing a critical region bounded by the critical edge and the polygon edge opposite the critical edge, comparing the critical region to a potential defect criterion, and generating as output a location of the critical region when the critical region satisfies the potential defect criterion.

Abstract: A method and apparatus are provided for generating and using timing constraints templates for IP cores that can be instantiated in an integrated circuit design. The templates include a plurality of timing constraint statements for inputs and outputs of the respective IP core. At least one of the statements includes a configurable variable, wherein the timing constraints template is configurable through the variable for each of a plurality of instances of the IP core in the integrated circuit design.

Abstract: The present invention is directed to methods for disabling unused IO resources in a platform-based integrated circuit. A slice is received from a vendor. The slice includes an IO circuit unused by a customer. The IO circuit is disabled. For example, when the IO circuit is desired to be tied to a power source, a primary input/output pin of the IO circuit is shorted to a power bus of the IO circuit. When the IO circuit is desired to be tied to a ground source, a primary input/output pin of the IO circuit is shorted to a ground bus of the IO circuit. When the IO circuit is desired to be left floated, a primary input/output pin of the IO circuit is not connected to any bonding pad cell of the slice. Next, the IO circuit is removed from the customer's logic design netlist. The IO circuit is inserted in the vendor's physical design database.

Abstract: A tributary time-space switch and a method of switching are provided having low memory requirements. The switch includes a number of inputs and outputs. Each of the inputs receives an input data stream carrying tributary payloads from an external input link that are capable of being individually switched in space and time. A write controller causes input columns of the input data stream to be written to a common buffer according to a write pointer. In parallel, a read controller causes the input columns to be read from the common buffer to output columns of an output data stream according to a read pointer. For each of the output columns, the read pointer selects an input column from a limited portion of the buffer that contains a set of the input columns that are capable of being switched in time to the corresponding output column according to a communication protocol.

Abstract: The present invention provides a memory BISR architecture for a slice. The architecture includes (1) a plurality of physical memory instances; (2) a Mem_BIST controller, communicatively coupled to the plurality of physical memory instances, for testing the plurality of physical memory instances; (3) a FLARE module, communicatively coupled to the Mem_BIST controller, including a scan chain of registers for storing test results of the plurality of physical memory instances, each of the plurality of physical memory instances M_i being assigned one FLARE bit f_i, i=1, 2, . . . , n, the FLARE module being used by the Mem_BIST controller to scan in an error vector F=(f—1, f—2, . . . , f_n); (4) a BISR controller, communicatively coupled to the FLARE module, a ROM module and a REPAIR_CONFIGURATION module, for scanning out the error vector F from the FLARE module to computer a repair configuration vector R=(r—1, r—2, . . .

Abstract: A interrogator 1 specifies the maximum read range (S0, e0) in which IDs to be read may exist (Step S1), and the interrogator 1 transmits a read request command to transponders 2 (Step S2. When there is/are a response/responses, it is judged if the response(s) is/are from a single transponder 2 or multiple transponders 2 (Step S5). When identifying multiple responses, an exponent e of the read range (S, e) is updated to e?=e?1 (Step S6). When identifying a single response, ID of the transponder 2 that responded is read out (Step S8) and the start S of the read range (S, e) is updated to S?=S+d (=2e) (Step S9). When a previous response flag F is not set to “multiple responses received”, the exponent e of the read range (S, e) is updated to e?=e+1 (Step S13).

Abstract: Methods and structure for improved import/export of RAID level 6 logical volumes in subsystems supporting RAID level 5 but not level 6. When a RAID level 6 logical volume is imported into a RAID level 5 storage subsystem, features and aspects hereof re-map the logical volume for use as a RAID level 5 logical volume. Disk blocks containing the level 6 additional redundancy information are not used by the RAID level 5 storage subsystem but are skipped in the re-mapping of the logical volume. All other blocks of the logical volume are mapped to corresponding blocks of the RAID level 6 mapping of the logical volume. The logical volume may then be flagged to indicate the additional redundancy information is invalid. A RAID level 6 storage subsystem may then rebuild the additional redundancy information when the flagged logical volume is re-imported to a RAID level 6 storage subsystem.

Abstract: An integrated circuit (IC) includes a strained-silicon layer formed by deposition of amorphous silicon onto either a region of a semiconductor layer that has been implanted with ions to create a larger spacing between atoms in a crystalline lattice of the semiconductor layer or a silicon-ion layer that has been epitaxially grown on the semiconductor layer to have an increased spacing between atoms in the silicon-ion layer. Alternatively, the IC includes a strained-silicon layer formed by silicon epitaxial growth onto the region of the semiconductor layer that has been implanted with ions. The IC also preferably includes a CMOS device that preferably, but not necessarily, incorporates sub-0.1 micron technology. The implanted ions may preferably be heavy ions, such as germanium ions, antimony ions or others. Ion implantation may be done with a single implantation process, as well as with multiple implantation processes.

Abstract: A method and sample for radiation microscopy include a sample source that includes an area of interest, an outer side of a sample formed in the sample source adjacent to the area of interest, an inner side of the sample formed inside the sample source wherein at least a portion of the area of interest is included between the inner side of the sample and the outer side, and a particle beam channel formed inside the sample source for conducting a particle beam to or from the inner side of the sample.

Abstract: The invention provides a number of related methods which improve the test and analysis of integrated circuit devices. A first method of the invention provides a method for pausing on a SCAN based test. A second method of the invention provides a method for using stimulations and responses of a known good device to increase fault coverage of patterns in a test flow. A third method of the invention provides a method to curve trace device buffers on an ATE.

Abstract: A set of tools is provided herein that produces useful, proven, and correct integrated semiconductor chips. Having as input either a customer's requirements for a chip, or a design specification for a partially manufactured semiconductor chip, the tools generate the RTL for control plane interconnect; memory composition, test, and manufacture; embedded logic analysis, trace interconnection, and utilization of spare resources on the chip; I/O qualification, JTAG, boundary scan, and SSO analysis; testable clock generation, control, and distribution; interconnection of all of the shared logic in a testable manner from a transistor fabric and/or configurable blocks in the slice. The input customer requirements are first conditioned by RTL analysis tools to quickly implement its logic. The slice definition and the RTL shell provides the correct logic for a set of logic interfaces for the design specification to connect. The tools share a common database so that logical interactions do not require multiple entries.

Abstract: The present invention is directed to improved dielectric copper barrier layer and related interconnect structures. One structure includes a semiconductor substrate having a copper line. An insulating layer formed of at least one of silicon and carbon is formed on the underlying copper line. An opening is formed in the insulating layer to expose a portion of the copper line. The inner surface of the opening in the insulating layer has a dielectric barrier layer formed thereon to prevent the diffusion of copper into the insulating layer. A copper plug is formed to fill the opening and make electrical contact with the underlying copper interconnect structure. Aspects of the invention also include methods for forming the dielectric copper barrier layers and associate copper interconnects to the underlying copper lines.

Abstract: Methods and associated structure for rapidly detecting a catastrophic failure of a bus structure within a storage subsystem. Features and aspects hereof associated with SCSI bus storage system configurations coordinate such failure detection with standard monitoring features of the SAF-TE enclosure monitoring specifications. In particular, standard polling operations of a SAF-TE compliant enclosure may be terminated early so as to preclude queuing additional polling related commands for disk drives or an enclosure of disk drives coupled to a SCSI bus cable or backplane that has experienced a catastrophic failure. Other features and aspects hereof disable all disk drives in a storage system that are coupled to a failed common bus.

Abstract: In some embodiments, a storage controller comprises a first input/output port that provides an interface to a host computer, a second input/output port that provides an interface a storage device, a processor that receives input/output requests generated by the host computer and, in response to the input/output requests, generates and transmits input/output requests to the storage device, and a memory module communicatively connected to the processor. The memory module comprises logic instructions stored in a computer-readable medium which, when executed by the processor, configure the processor to receive, from the host computer, a write input/output request that identifies a logical volume; compare an amount of storage space available in the logical volume with an amount of storage space required to complete the write operation, and allocate additional storage space to the logical volume if the amount of storage space available in the logical volume is insufficient to complete the write operation.

Abstract: A method for storing data, comprising the steps of (A) receiving a stream of data, (B) storing the stream of data in a series of data clusters each comprising (i) a predecessor link, (ii) a data portion, and (iii) a successor link, where the predecessor links and successor links are configured to minimize seek time between the clusters during contiguous stream operations.

Abstract: The design of integrated circuits, i.e., semiconductor products, is made easier with a semiconductor platform having versatile power mesh that is capable of supporting simultaneous operations having different frequencies on the semiconductor product; e.g., higher frequency operations may be embedded as diffused blocks within the lower layers or may be programmed from a configurable transistor fabric above the diffused layers. Preferably the power mesh is located above the layers having the operations requiring the different frequencies, and may be fixed in an application set given to a chip designer or may be configurable by the designer her/himself. For example, to support high speed communications adjacent an embedded high speed data transceiver, the transistor fabric may be programmed as a data link layer having higher performance requirements than the rest of the integrated circuit.

Abstract: A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.

Abstract: A random number generator includes a ring oscillator having an EX-OR gate and four inverters together forming a loop. This loop enters stable state for a start signal having the low level and oscillates for the start signal having the high level. When the start signal has a pulse of a width shorter than the loop's delay time, output nodes responsively, sequentially enter metastable state hovering between the high and low levels. The metastable waveform becomes smaller with time and finally disappears. As metastable state cannot be controlled in longevity, it disappears at any random number node. A counter thus outputs a signal serving as true random number data depending on the longevity of the metastable state. A random number generator miniaturized and having reduced power consumption, and of high performance can thus be implemented.

Abstract: The invention is a method and system for applying more effects to voices in an input sound than is capable of being supported by a sound processor. Aspects of the invention include identifying at least one of the voices of the input sound as a voice bus channel; and during processing of the input sound, inputting and adding sound that was mixed from outputs of previously processed voices to the voice bus channel to create a summed result. An effect specified for the voice bus channel is then applied to the summed result, thereby applying the effect to the previous the process voices.