Abstract: A method and apparatus are provided for receiving a list of design memories, wherein each type of design memory in the list has a name and at least one instance. A pre-placement model is associated with each named memory type in the list. The design memories in the list are mapped to an integrated circuit layout pattern, wherein at least one memory type comprises first and second instances that are mapped differently from one another. After mapping, at least one of the first and second instances is renamed to have a different name than the other. A post-placement model is then associated with each named memory type in the list, including a separate model for each renamed design memory.
Type:
Grant
Filed:
November 16, 2005
Date of Patent:
September 9, 2008
Assignee:
LSI Corporation
Inventors:
Alexandre Andreev, Andrey Nikitin, Ilya V. Neznanov, Ranko Scepanovic
Abstract: A graphical profile map for integrated circuits on a substrate. The graphical profile map includes a depiction of die placement boundaries and shot placement boundaries for the integrated circuits on the substrate. Also included are integrated circuit property information contours, where the contours are not limited to either of the die placement boundaries or the shot placement boundaries. In this manner, three key pieces of information for the integrated circuits are presented, including integrated circuit property information, die placement, and shot placement. Because these three pieces of information are presented in a graphical form, it is much easier to interpret the information. For example, it is much easier to determine which shot and die placements have properties that are at risk, and which shot and die placements have adequate property profiles.
Type:
Application
Filed:
May 8, 2008
Publication date:
September 4, 2008
Applicant:
LSI CORPORATION
Inventors:
ChandraSekhar Desu, Nima A. Behkami, Bruce J. Whitefield, David A. Abercrombie, David J. Sturtevant
Abstract: An apparatus comprising a first circuit, a second circuit, a third circuit and a fourth circuit. The first circuit may be configured to generate a demodulated signal in response to (i) a modulated signal and (ii) a seed value. The second circuit may be configured to generate a first control signal in response to the demodulated signal. The third circuit may be configured to generate a second control signal in response to (i) the first control signal and (ii) a compensation signal. The fourth circuit may be configured to generate the seed value in response to the second control signal.
Abstract: A test vehicle for evaluating a manufacturing process for integrated circuits that uses a more space efficient layout of library driving cells arranged to produce circuits that exercise many interconnections that may be designed at the minimum design parameters of a manufacturing process. The cells can be configured to operate as ring oscillators increasing the effective circuit frequency of the test module allowing higher frequency circuit testing, and shortening the time it takes to perform life cycle testing. Visibly marking cells, combined with electrically isolating error prone circuit segments makes, identifying defects much more efficient. The accessibility of many testing methods allows quick location of root cause failures, which allows improvements to be made to the manufacturing process.
Abstract: Disclosed is a system and method for transmitting computer data within a single computer system along more than one physical data path by providing a multiple-path driver that creates virtual (or non-physical) data paths without modifying the source code of the operating system. The system and method may be used with any computer hardware regardless of manufacturer. In one embodiment, a multiple-path driver may be used within a Linux operating system to create virtual data paths and transmit data between the upper-level drivers of the Linux system and at least one computer data storage device without modifying the Linux source code.
Abstract: A method for encoding video, comprising the steps of (A) detecting repeated fields in a video sequence and (B) generating a first repeated frame from a top field and any adjacent bottom field based upon detection of the repeated fields, wherein the top field and the bottom field are from one film frame.
Abstract: An integrated circuit (IC) package comprises a package substrate, an IC die mounted on the package substrate, a wire bond electrically connecting the IC die and the package substrate, and a heat spreader mounted on the package substrate. The heat spreader comprises a hole through a portion thereof. The IC die and the wire bond are disposed substantially between the heat spreader and the package substrate.
Type:
Grant
Filed:
June 22, 2004
Date of Patent:
September 2, 2008
Assignee:
LSI Corporation
Inventors:
Hong T. Lim, Maurice O. Othieno, Qwai H. Low
Abstract: Methods and structure for improved import of RAID level 6 logical volumes into subsystems devoid of RAID level 6 hardware support. When a RAID level 6 logical volume is exported from a first storage subsystem and imported into a second storage subsystem devoid of RAID level 6 hardware support, features and aspects hereof first migrate the logical volume for use as a logical volume with a different RAID level supported by the second storage subsystem. The migration may be, for example, to a RAID level 5 logical volume performed by movement of data blocks to form new stripes and re-generation of associated parity blocks or by simpler re-mapping of existing blocks of the RAID level 6 volume to use only blocks and parity needed for RAID level 5 management. Further features and aspects allow migration to any other RAID management level supported by the second storage subsystem.
Abstract: A method and apparatus extract information from a burst cutting area (BCA) of a recording medium. The BCA extraction includes (a) receiving a signal from the recording medium, the signal including BCA data read from the BCA, the BCA data being represented by channel symbols, (b) analog-to-digital (A/D) sampling the signal to generate input data, (c) identifying a BCA region within the input data, the BCA region corresponding to the BCA data, (d) determining an average channel symbol width of the BCA data, the average channel symbol width corresponding to an average number of A/D samples per channel symbol in the BCA data, (e) increasing a signal-to-noise ratio (SNR) of the BCA data using the average channel symbol width, (f) generating a channel pattern data from the BCA data using a selected threshold value, and (g) generating a channel symbol data from the channel pattern data using the average channel symbol width.
Abstract: A method for detecting and controlling disc tilt in an optical disc mechanism comprising the steps of (A) measuring a 2-dimensional displacement of an optical lens of the optical disc mechanism, (B) extracting an absolute value of a disc tilt angle in the optical disc mechanism based upon the 2-dimensional displacement and (C) controlling deflection of a tilt moving coil according to the absolute value of the disc tilt angle.
Abstract: A boot menu is provided for manual setting of serial port parameters. A serial console mode menu allows an operator to set serial port parameter values. After the user selects the serial port parameters, when the controller continues with the boot process, the serial port is initialized with the newly selected parameters. A mechanism is also provided for manual setting of serial port parameters through an administrative management window at the host. In addition, an adaptive baud rate negotiation mechanism using the Universal Asynchronous Receiver Transmitter (UART) registers in the serial port is provided. The adaptive baud rate negotiation is based on the return characters received from a break character from the serial console. The mechanism uses a look-up table for the baud rate versus the bit pattern that is received. The mechanism then sets the baud rate based on the look-up table values.
Abstract: A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.
Type:
Grant
Filed:
December 19, 2005
Date of Patent:
August 19, 2008
Assignee:
LSI Corporation
Inventors:
Alexander Andreev, Anatoli A. Bolotov, Ranko Scepanovic
Abstract: A method of placing and routing an integrated circuit design includes generating an initial placement and routing for at least a portion of an integrated circuit design. The initial placement and routing of the integrated circuit design is analyzed to find a critical location and is partitioned into a series of nested shells. Each shell surrounds the critical location and each preceding shell. An ordering of the shells and at least one of a timing constraint and an area constraint are selected for each shell. Each shell is placed and routed in the order selected according to the timing constraint and area constraint.
Type:
Grant
Filed:
October 5, 2005
Date of Patent:
August 19, 2008
Assignee:
LSI Corporation
Inventors:
Juergen K. Lahner, Balamurugan Balasubramanian, Randall P. Fry
Abstract: A method of forming a high k gate insulation layer in an integrated circuit on a substrate. A high k layer is deposited onto the substrate, and patterned with a mask to define the high k gate insulation layer and exposed portions of the high k layer. The exposed portions of the high k layer are subjected to an ion implanted species that causes lattice damage to the exposed portions of the high k layer. The lattice damaged exposed portions of the high k layer are etched to leave the high k gate insulation layer.
Abstract: Embodiments of the invention include a method for forming a copper interconnect having a bi-layer copper barrier layer. The method comprises the steps of providing a substrate with a low-K dielectric insulating layer and an opening in the insulating layer. A first barrier layer of tantalum/tantalum nitride is formed on the insulating layer and in the opening. A second barrier layer consisting of a material selected from the group of palladium, chromium, tantalum, magnesium, and molybdenum is formed on the first barrier layer. A copper seed layer is formed on the second barrier layer and implanted with barrier ions and a bulk copper layer is formed on the seed layer. The substrate is annealed and subject to further processing which can include planarization.
Type:
Grant
Filed:
April 10, 2007
Date of Patent:
August 19, 2008
Assignee:
LSI Corporation
Inventors:
Wilbur G. Catabay, Zhihai Wang, Ping Li
Abstract: An in-line, in-process or in-situ and non-destructive metrology system, apparatus and method provides composition, quality and/or thickness measurement of a thin film or multi-layer thin film formed on a substrate in a thin film processing system. Particularly, the subject invention provides a spectroscopic ellipsometer performing spectroscopic ellipsometry while the wafer is in a thin film processing system. In one form, the spectroscopic ellipsometer is associated with a wet bench system portion of the thin film processing system. The spectroscopic ellipsometer obtains characteristic data regarding the formed thin film to calculate penetration depth (Dp) for a thin film formed on the substrate. Particularly, the ellipsometer obtains an extinction coefficient (k) which is used to calculate penetration depth (Dp). Penetration depth (Dp), being a unique function of the extinction coefficient (k) provides the information for the composition, quality and/or thickness monitoring of the thin film.
Abstract: A method for activating and deactivating parameter sets comprising the steps of: (A) activating a first parameter set in response to a reference to a first identification value associated with the first parameter set and (B) deactivating the first parameter set in response to a reference to a second identification value associated with a second parameter set.
Abstract: The embodiments of the present invention are directed toward the design of routing patterns, including elements such as contacts, traces, and vias, for high speed differential signal pairs in integrated circuit package substrates.
Abstract: The present invention is a method and system for outputting a sequence of commands and data described by a flowchart. In an exemplary aspect of the present invention, a method for outputting a sequence of commands and data described by a flowchart includes steps as follows. A flowchart describing a sequence of commands and data is received. The flowchart includes a plurality of flowchart symbols. Each of the plurality of flowchart symbols is assigned a ROM (read only memory) record. Assigned ROM records are stored in a ROM. A module (e.g., a CKD, or the like) is generated to include the ROM, wherein the module receives as input a CLOCK signal, a RESET signal, an ENABLE signal and N binary inputs x1, x2, . . . xN, and outputs the sequence of commands and data.
Type:
Grant
Filed:
July 20, 2004
Date of Patent:
August 19, 2008
Assignee:
LSI Corporation
Inventors:
Alexander E. Andreev, Andrey A. Nikitin, Ranko Scepanovic
Abstract: A menu panel for supporting elongated menu strips of varying heights is disclosed having adjustable guide rails supported by a frame. The frame includes vertical side frame members incorporating guide rail locating elements disposed along the length of the vertical side frame members to position the guide rails. The guide rails are selectively positionable along the length of the vertical side frame members to provide adjustable spacing between adjacent pairs of guide rails. The menu strips include descriptive indicia such as product names and pricing information and are disposed between and supported by adjacent pairs of the guide rails.
Type:
Grant
Filed:
December 20, 2004
Date of Patent:
August 19, 2008
Assignee:
LSI Industries, Inc.
Inventors:
James E. Bradley, Donald E. Lunnemann, Robert Uzzolino