Abstract: A method of buffer insertion for a tree network in an integrated circuit design includes steps of: (a) receiving as input an integrated circuit design including a tree network; (b) selecting a buffer type available to the integrated circuit design from a cell library that results in a minimum total delay for a predetermined wire length; (c) identifying each candidate leaf node in the tree network that has a required pin-specific target delay; (d) inserting a buffer between each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network and each leaf node that is not a candidate leaf node; (e) creating a buffer sub-tree in the tree network from an upstream internal node for each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network; re-parenting each internal node that is traversed by a path from a candidate leaf node to a root node of the tree network to a new buffer in the buffer sub-tree; and (g) generating as out

Abstract: The present invention has an object to enrich expression of contents of an e-mail message. In a mobile phone (1), text data (TxD) is input, and a 3D authoring operation is carried out. The text data (TxD) and 3D authoring instruction data (DD) are transmitted from the mobile phone (1) to a server (3), and then, scenario data (SD) which is control information about 3D graphics is generated in the server (3). The text data (TxD) and scenario data (SD) are stored in the server (3) as 3D message information (MD). When access information to the 3D message information (MD) is notified from the mobile phone (1) to a mobile phone (2), the mobile phone (2) makes access to the server (3) to download the 3D message information (MD) and a necessary 3D font. 3D character mail is thereby reproduced in the mobile phone (2).

Abstract: Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. In one aspect, a duty cycle controller is coupled to the signal pad for balancing a duty cycle of the first signal with respect to a clock signal. In another aspect, dynamic switchable termination is coupled to the signal pad for providing termination impedance when the I/O cell is receiving the second signal.

Abstract: An external scan test module that is adapted to act as an interface between an automated tester and a device under test. The external scan test module includes a scan pattern memory to hold scan patterns for at least one configuration of the device under test. A failure log memory holds failure information for the device under test. A controller sends scan input data to the device under test, receives scan output data from the device under test, and sends and receives signals from the automated tester. An interface receives scan patterns.

Abstract: The present invention is directed to a method and system for high bandwidth fault tolerance in a storage system while the system, maintaining dual parity scheme, may tolerate the failure of more than one disk. An array controller may comprise a parity buffer sufficiently large enough to hold all of the parity blocks for an entire stripe of data. This may provide for high bandwidth fault tolerance without reading the source blocks twice while the dual parity values are calculated using two different/independent parity computations for a given stripe. Such a dual parity scheme may allow the storage system to tolerate the failure of more than one disk.

Abstract: A file management information area of a memory includes a FAT and a replacement information table. In the FAT, chain information on a file is recorded and in the replacement information table, replacement information of a defective area is recorded. In order to read out the file, a file system reads out the FAT and the replacement information table to generate indexes of the file and stores the indexes to an index buffer. In a memory controller, an address part of a read command is sequentially replaced with indexes stored in the index buffer and page-replaced read commands are continuously transferred to the memory.

Abstract: A similar-image detecting part detects similar image regions similar to one another in a plurality of frame images captured by rolling shutter type exposure. A displacement-vector detecting part detects a displacement vector of each of the similar image regions with respect to a reference position in each of the plurality of frame images. An average calculating part calculates an average of displacement vectors in the plurality of frame images. A correcting part shifts a similar image region in one of the plurality of frame images such that the displacement vector of the similar image region becomes the average calculated by the average calculating part.

Abstract: Pixel signals are sequentially output from an image sensor in a reverse order to an order in which light sensing cells are arranged with respect to one of a horizontal direction and a vertical direction. In an image processor, first, a data reading part transfers the pixel signals in the same order as corresponding light sensing cells are arranged with respect to both of a horizontal direction and a vertical direction, and a signal sequence of the pixel signals is changed. Then, the pixel signals which are output group by group are sequentially selected by a selector in accordance with a sequence of groups. As a result, the pixel signals can be supplied from the selector in an order conforming a two-dimensional array of the light sensing cells, to thereby facilitate color interpolation which is to be later performed by a color interpolator.

Abstract: The present invention provides an endian mapping engine for use with a processing system. In one embodiment, the endian mapping engine includes an identification unit configured to identify sending and receiving endian schemes for data transfers between components of the processing system. Additionally, the endian scheme converter also includes a conversion unit coupled to the identification unit and configured to convert the data transfers between the sending and receiving endian schemes corresponding to an employed endian format. In an alternative embodiment, the endian mapping engine further includes a multiplexing unit coupled to the identification unit and configured to provide multiplexing between endian formats for a given endian scheme.

Abstract: A circuit generally comprising a multiport memory, a direct memory access engine and a programmable gate array is disclosed. The direct memory access engine may be configured to transfer a first program to the multiport memory. The programmable gate array may be configured to (i) load the first program directly from the multiported memory to program a codec function and (ii) generate a video output signal by performing the codec function on a video input signal using video data exchanged with the multiport memory.

Abstract: The present invention optimizes the dynamic power characteristics of an integrated circuit (IC) chip. The IC chip includes a plurality of layers, wherein at least one of the layers is a power mesh layer that provides power to the IC chip, and includes a ground (Vss) net. The method includes providing at least one dummy metal mesh layer, and coupling the dummy metal mesh layer to the Vss net on the power mesh layer thereby increasing the capacitance on the Vss net.

Abstract: An apparatus and method for filtering glitches in data signals are provided. The apparatus and method provide a programmable glitch filter that may be programmed to filter glitches of different depths. The apparatus and method further provide a glitch filter that is programmable and incorporates a synchronizer for synchronizing the filtered output from the glitch filter to a different clock domain than that of the clock input.

Abstract: A method for recovering data from a redundant storage object comprises a command, executable upon a redundant storage object, which provides a mechanism for discovering the existence of copies of the data image and the number of copies of the data image available. The present invention further provides the capability of retrieving a copy of the data image(s) from underlying virtualization layers. By querying specific layers of the IO path to determine if a specific layer has copies of the data image, the number of copies may be determined and specified copies of the data image retrieved. This allows higher layers within a system to perform recovery if incorrect data is detected.

Abstract: A method and apparatus for traversing a queue of commands containing a mixture of read and write commands places a Next Valid Write Address pointer in each queue entry. In this manner, time savings are achieved by allowing preprocessing of the next write command to be executed. The method may be practiced by setting a next valid address pointer in all queue entries. Queue traversal may be forward, backward, or bi-directional.

Abstract: A surgical crimping instrument for crimping a sleeve including an anvil and a hammer moveable relative to each other to crimp the sleeve, a pusher movable longitudinally and engaging the hammer and/or anvil for urging the hammer and the anvil together as the pusher moves longitudinally from a first position to a second position, and cooperative stops adjacent to the hammer and the anvil for limiting the relative movement of the hammer towards the anvil.

Abstract: The present invention is directed toward systems, packages, and methods for providing improved thermal performance in such packages and systems. Embodiments of the invention include a semiconductor integrated circuit (IC) package having a substrate with a heat spreader mounted on the substrate. An IC die is mounted to the heat spreader such that the heat spreader lies in between the die and the substrate. The invention is also directed to a heat spreader plate useable in a semiconductor package. The heat spreader plate comprises a plate comprised of thermally conductive material suitable for attachment to a packaging substrate wherein the plate includes openings for exposing electrical bonding surfaces of a packaging substrate when the heater spreader plate is mounted on the packaging substrate. Such openings enable wirebonding between the exposed electrical bonding surfaces of the substrate and an integrated circuit die to complete construction of a package including the heatspreader.

Abstract: A memory timing model is provided, which includes an address input, a multiple-bit data input, a multiple-bit data output, a capacity C and a width N. N one-bit wide memory modules are instantiated in parallel with one another between respective bits of the data input and the data output. Each memory module has a capacity of C bits addressed by the address input.

Abstract: A method and apparatus calculate resistance of a three-dimensional conductor system defined by boundary faces. The resistance calculation includes (a) partitioning the three-dimensional shape into a plurality of parallelepipeds, a boundary between two parallelepipeds forms and entire face for both of the two parallelepipeds, (b) determining at least one source face and at least one sink face from among the boundary faces, a current entering the conductor system through the source face and leaving the conductor system through the sink face, (c) setting boundary conditions with respect to the current for each of the parallelepipeds, (d) calculating power for each of the parallelepipeds with the boundary conditions, (e) calculating power for the conductor system based on the power and the boundary conditions of each of the parallelepipeds, and (f) obtaining the resistance of the conductor system by minimizing dissipation of the calculated power of the conductor system.

Abstract: A time division media access controller for use with a multi-port data switch and a method of controlling media access. In one embodiment, the time division media access controller includes a time division receive engine, a time division transmit engine and a time division arbiter coupled to the time division receive and transmit engines. The time division receive engine accepts data from a plurality of data ports and the time division transmit engine provides data to a plurality of data ports. The time division arbiter controls states of the time division receive and transmit engines based on throughput requirements of the data. In preferred embodiments, the time division media access controller complies with the IEEE 802.3 ethernet standard.

Abstract: A disclosed memory, such as a random access memory (RAM) has multiple banks including a first bank and a second bank each having multiple latch cells configured to store data. The first bank has a first bit line, and the second bank has a second bit line. A first tri-state buffer has an input node coupled to the first bit line, an enable node coupled to receive a first enable signal, and an output node coupled to a tri-state bit line. A second tri-state buffer has an input node coupled to the second bit line, an enable node coupled to receive a second enable signal, and an output node coupled to the tri-state bit line. Enable signal generation logic uses a portion of an address signal to generate the first and second enable signals such that the first and second enable signals are not in an active state simultaneously.