Abstract: An apparatus comprising a first processing circuit and a second processing circuit. The first processing circuit may be configured to generate a motion vector residual in response to one or more macroblocks of an input signal. The second processing circuit may be configured to convert between (i) the motion vector residual and (ii) a binarized representation of the motion vector residual. The binarized representation of the motion vector residual generally comprises (i) a binarized representation of an absolute value of the motion vector residual and (ii) a binarized representation of a sign of the motion vector residual when the motion vector residual has a non-zero value. The binarized representation of the sign is generally located after an end of the binarized representation of the absolute value of the motion vector residual.

Abstract: In a memory, a file is stored at discontinuous page addresses. The information thereon is recorded in FAT of the memory. When an application program in a host system performs a read operation for the file, a FAT system refers to the FAT to read out page indexes of the file. Then, the page indexes are stored in a page index buffer included in a memory controller. When a DMAC outputs a read command, a page index transfer sequencer replaces an address part of this read command with the page indexes and outputs page-replaced read commands to the memory.

Abstract: A method and apparatus are provided for creating and using a memory timing database. A plurality of characterization memories are defined, which can be mapped to a memory resource. Each characterization memory has different memory parameters. A plurality of variants of tiling each characterization memory to the memory resource are also defined. Timing characteristics of each tiling variant of each characterization memory are stored in the memory timing database for the memory resource based on sets of input ramptimes and output loads.

Abstract: A search engine architecture substitutes short indices for large data widths, thereby reducing widths required for input to and output from the search engine. The search engine system comprises a search engine responsive to an input address to access an index in the search engine. The index has a width no greater than logarithm on base 2 of the search engine capacity, thereby permitting the search engine to be embodied in an IC chip of reduced area. A driver responds to input commands and to the search engine status to manage indices in the search engine and enable the memory to access its addressable locations based on indices in the search engine.

Abstract: A method and apparatus for testing latch based random access memory includes steps of generating a scan enable signal for testing latch based random access memory and generating a scan clock signal for testing the latch based random access memory wherein the scan clock signal has a first scan clock period for a shift cycle and a second scan clock period for a capture cycle.

Abstract: A debugging tool for computer program development that analyzes the computer program adds output statements at strategic locations throughout the program. The output statements may include the filename and line number of the original source code and may further include a listing of the executed command as well as values of certain expressions and/or variables as defined by the requested verbosity. The verbosity may be set at different levels throughout the source code as required.

Abstract: A method of implementing an engineering change order includes steps of: (a) receiving as input an integrated circuit design; (b) receiving as input an engineering change order to the integrated circuit design; (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; (d) performing a routing of the integrated circuit design that excludes routing of any net that is not enclosed by the window; (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and (f) generating as output the revised integrated circuit design.

Abstract: A method and apparatus are provided for placing cells in an integrated circuit layout pattern. A base layer layout pattern defines an array of base cell locations and base layer elements, wherein at least portions of some rows in the array are reserved for decoupling capacitor cells. Each decoupling capacitor cell has a width, which is greater than that of a single base cell location and which is abstracted from the base layer layout pattern. A cell library defines a plurality of cells, including a macro cell having open rows consistent with the rows in the base layer layout pattern that are reserved for the decoupling capacitor cells. The width of each decoupling capacitor cell is abstracted from the macro cell. Cells from the cell library, including the macro cell, are placed within a design layout pattern relative to the base layer layout pattern. An area consumed by the macro cell within the design layout pattern is independent of the width of the decoupling capacitor cells.

Abstract: Techniques or designs of circuits to correct distortions in signals transported over a high-speed digital connection between a video source (e.g., a PC or a DVD player) and a digital monitors (such as LCDs) are disclosed. According to one aspect of the present invention, a distorted signal is corrected by an interface circuit that oversamples the incoming signal with clock pulses or signals generated using a phase lock loop (PLL) from a clock seed signal. These clock signals possess different phases that are shifted from each other. In order to support a wide range of data rate, a programmable DPLL is used to produce a number of different ranges of clock frequency (e.g., 4 ranges). In addition, to avoid data phase shift, a delay locked loop (DLL) is used to compensate for the phase shift. A phase detection logic is also used to extract phase information from the over-sampled data. The phase information is fed back to the DLL.

Abstract: Methods for forming robust copper structures include steps for providing a substrate with an insulating layer with openings formed therein. At least two barrier layers are then formed followed by the deposition of a copper seed layer which is annealed. Bulk copper deposition of copper and planarization can follow. In one approach the seed layer is implanted with suitable materials forming an implanted seed layer upon which a bulk layer of conductive material is formed and annealed to form a final barrier layer. In another approach, a barrier layer is formed between two seed layers which forms a base for bulk copper deposition. Another method involves forming a first barrier layer and forming a copper seed layer thereon. The seed layer being implanted with a barrier material (e.g. palladium, chromium, tantalum, magnesium, and molybdenum or other suitable materials) and then bulk deposition of copper-containing material is performed followed by annealing.

Abstract: A method for processing an input signal is disclosed. The method generally includes the steps of (A) extracting a compressed signal and a first checksum from the input signal, (B) generating a decompressed signal by decompressing the compressed signal, (C) calculating a second checksum for the decompressed signal and (D) generating a result by comparing the first checksum to the second checksum.

Abstract: A method, computer program product, and apparatus for efficiently utilizing software licenses in a large organization having multiple divisions is disclosed. A preferred embodiment of the present invention accomplishes this goal by providing for a pool of organization-wide software licenses. This license pool is subdivided into a number of reserved or dedicated licenses for each particular division and a set of shared licenses to be shared among the various divisions. A given division, when checking out licenses from the organization-wide pool, will first exhaust its reserved licenses before checking out shared licenses. In the event that all shared licenses are being used, but there are reserved licenses that are sitting idle, a division may borrow a reserved license from another division, subject to the lending division's right of preemption in the event that the borrowed license is needed by the division lending the license.

Abstract: A circuit for parametric testing of an integrated circuit includes an integrated circuit having a plurality of input buffers and a plurality of XOR gates. The plurality of XOR gates have a first input that is connected to an output of one of the input buffers and having a second input that is connected to an output of a preceding XOR gate to form an XOR logic tree.

Abstract: Disclosed is an object oriented netlist database that stores electrical circuit data parsed from a netlist text file that is formatted in HSPICE or Circuit Design Language (CDL) formats. To obtain the netlist text file, an electrical circuit schematic of an electrical circuit is created using a commercially available electrical schematic capture software tool. The electrical schematic capture software tool is then directed to create the netlist text file that is representative of the electrical circuit. A netlist text file parser program first creates the object oriented netlist database structure, then parses the netlist text file, and finally fills the netlist database with objects that represent the electrical circuit data contained in the netlist text file. Analysis software may be written to programmatically access the electrical data stored in the netlist database using netlist database access subroutines that are part of the netlist database objects.

Abstract: Correlation values in the vertical direction, horizontal direction and two diagonal directions are obtained in a pixel signal of RGB Bayer pattern. The correlation values are calculated using G signals. Between a first pair of the vertical and horizontal directions and a second pair of the two diagonal directions, one pair having a greater correlation difference is selected. Then, a direction having a stronger correlation is selected in the selected pair having a greater correlation difference, and pixel interpolation is performed in the selected direction. Alternatively, pixel interpolation is performed following assignment of weights in two directions of the selected pair having a greater correlation difference in accordance with the proportion of their correlations.

Abstract: A system and method are described for increasing performance of operations implemented in a storage system utilizing fibre channel, such as by enabling full duplex opens when a JBOD/bridge is involved. In an aspect of the present invention, a method of performing a full duplex open in a fibre channel network having an initiator and a bridge may include initiating an open by the initiator with the bridge. The bridge has a primary physical address and an alias physical address. The alias physical address represents a target device communicatively coupled to the bridge, wherein the open is initiated utilizing the primary physical address. The initiator communicates with the target device.

Abstract: A circuit generally comprising a logic module and a security module is disclosed. The logic module may be configured to set a plurality of values to a plurality of predetermined values respectively while in a scan mode. The security module may be configured to (i) disable a scan capability of the values while in a non-lowest security mode of at least three security modes and (ii) enabling the scan capability while in a lowest security mode of the security modes.

Abstract: A method for accounting for negative bias temperature instability in a rise delay of a circuit design, the method comprising the steps of create a cell and net model library with original rise numbers, construct the circuit design from the cell and net models, for each cell and net in the circuit design, calculate an original rise delay, apply a negative bias temperature instability model to determine a parameter shift, determine a new rise number from the parameter shift, and calculate a new rise delay by original rise delay* (original rise number)/(new rise number).

Abstract: A motion detecting part detects moving regions in a plurality of frame images captured by rolling shutter type exposure, and obtains a motion vector of the moving regions. A moving region correcting part corrects the moving region in a to-be-corrected frame image of the plurality of frame images on the basis of the motion vector, information on an image-capturing time interval between the plurality of frame images, information on an exposure starting time difference resulting from the difference in position in one frame image caused by the rolling shutter type exposure and information on an exposure start sequence depending on the position in one frame image captured by the rolling shutter type exposure.

Abstract: The present invention is test structures in unused areas of semiconductor integrated circuits and methods for designing the same. In an exemplary aspect of the present invention, a method for placing test structures in a semiconductor integrated circuit includes: (a) detecting a dummy area in a semiconductor integrated circuit, the semiconductor integrated circuit including probe pads on a top metal layer; (b) filling the dummy area with active test cells, the active test cells being connected to one another; and (c) connecting each of the active test cells to the probe pads with a metal line.