Patents Assigned to LSI
  • Twin MONOS array metal bit organization and single cell operation
    Patent number: 6631088
    Abstract: In the present invention a twin MONOS metal bit line array is read and programmed using a three dimensional programming method with X, Y and Z dimensions. The word line address is the X address. The control gate line address is a function of the X and Z addresses, and the bit line address is a function of the Y and Z addresses. Because the bit lines and the control gate lines of the memory array are orthogonal a single cell can be erased with an adjacent memory, having the same selected bit and control gate lines, being inhibited from erase by application of the proper voltages to unselected word, control gate and bit lines.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: October 7, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoya Saito, Tomoko Ogura
  • Standard high volume battery charger
    Patent number: 6630812
    Abstract: The present invention is directed to a standard high volume battery charger that is capable of applying a seasoning cycle to batteries disposed within it as well as display battery measurements on a monitor through a user interface serial port. This battery charger comprises an enclosure including a power supply, a user interface connector and disposed with at least one sub-module comprising a mode control board and battery cavity. The mode control board has a user interface front panel, which is comprised of a battery section, battery status panel and a system status panel. The system status panel has disposed upon it two switches, that control the operation of the sub-module, which enable a user to select the application of a seasoning cycle to the batteries in the charger.
    Type: Grant
    Filed: May 2, 2002
    Date of Patent: October 7, 2003
    Assignee: LSI Logic Corporation
    Inventor: Laurel B. Davis
  • System for packet communication where received packet is stored either in a FIFO or in buffer storage based on size of received packet
    Patent number: 6631484
    Abstract: An interface apparatus provides a connection between a host having an IEEE 1394 input/output port and a mass storage device having an ATA input/output port. A receive FIFO and a transmit FIFO within the interface apparatus operates to store small-size packets, or operates to store the buffer address of large-size packets, as the small and large size packets are respectively received from the host or transmitted to the host. In both the host receive and host transmit modes of operation of the interface apparatus, the small-size packets are found in the receive FIFO or the transmit FIFO, whereas the data content of large-size packets is stored in the buffer as the corresponding buffer address is stored in the receive FIFO or the transmit FIFO.
    Type: Grant
    Filed: March 31, 1998
    Date of Patent: October 7, 2003
    Assignee: LSI Logic Corporation
    Inventor: Richard M. Born
  • Field freeze filter implementation
    Patent number: 6630965
    Abstract: A circuit for freezing a video frame having a first field interlaced with a second field. The circuit generally comprises a memory and a filter. The memory may be configured to present a plurality of coefficient signals that define (i) a first coefficient set for the first field and (ii) a second coefficient set for the second field. The filter may be configured to present a new frame in place of the video frame. The new frame may be generated from either (i) the first field and the first coefficient set in response to freezing on the first field or (ii) the second field and the second coefficient set in response to freezing on the second field.
    Type: Grant
    Filed: February 27, 2001
    Date of Patent: October 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Ning Xue, Darren D. Neuman, Gregg Dierke
  • Microcomputer timing control circuit provided with internal reset signal generator triggered by external reset signal
    Patent number: 6631467
    Abstract: A microcomputer has an internal reset signal generator for generating an internal reset signal from an external reset signal supplied via a chip reset input terminal. The internal reset signal generator includes a first two-input logic circuit that has its first gate input terminal connected to the chip reset input terminal and outputs a low-level first logic signal only when its two gate input terminals are placed at a high level. The first logic signal is inverted by an inverter and is supplied to the second gate input terminal of the first two-input logic circuit. The second gate input terminal is pulled up by a capacitor connected to a higher power supply voltage terminal. The external reset signal and the first logic signal are supplied to a second two-input logic circuit that changes the level of the reset signal only when both the inputs are at the high level.
    Type: Grant
    Filed: August 7, 2000
    Date of Patent: October 7, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventor: Taiyuu Miyamoto
  • Server for operation with a low-cost multimedia terminal
    Patent number: 6631418
    Abstract: A server for providing personal computer (PC) functionality to a user at a multimedia terminal processes commands from the user. The server includes a source upgrade processor, a client software component for receiving a command signal from the user, a display updater for combining signals and a video encoder for sending a digital audio/visual (A/V) data-stream to a multimedia terminal. The server enables concurrent computer application processing for multiple simultaneous thin client users each having a multimedia terminal using a communication link to connect them to the server.
    Type: Grant
    Filed: April 5, 2000
    Date of Patent: October 7, 2003
    Assignee: LSI Logic Corporation
    Inventor: Daniel Watkins
  • Microcomputer including system for controlling and maintaining the electric potential of an input terminal to improve interrupt response time
    Patent number: 6631475
    Abstract: A microcomputer has an electric potential control unit, a signal generation unit, and a timing signal generation circuit. The electric potential control unit includes a transistor which controls an electric potential of an input terminal which is energized by a power supply. The signal generation unit includes an input buffer circuit which receives a change in the electric potential of the input terminal and supplies an interrupt signal to a CPU. The timing signal generation circuit generates a timing signal which controls conductivity of a transistor and operates the transistor intermittently. A capacitor is connected to the input terminal.
    Type: Grant
    Filed: August 3, 2000
    Date of Patent: October 7, 2003
    Assignees: Mitsubishi Denki Kabushiki Kaisha, Mitsubishi Electric System LSI Design Corporation
    Inventors: Hiroyuki Nagayama, Hironari Yoshida
  • Bit line decoding scheme and circuit for dual bit memory array
    Patent number: 6631089
    Abstract: In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.
    Type: Grant
    Filed: July 8, 2002
    Date of Patent: October 7, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Nori Ogura, Tomoko Ogura
  • Method and apparatus for removing water vapor as a byproduct of chemical reaction in a wafer processing chamber
    Patent number: 6630411
    Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.
    Type: Grant
    Filed: May 7, 2002
    Date of Patent: October 7, 2003
    Assignee: LSI Logic Corporation
    Inventors: Robert D. Broyles, Michael J. Berman
  • Reduced particulate etching
    Publication number: 20030186550
    Abstract: A platen for use in a dry etching process for substrate production, the platen having a surface susceptible to chipping and/or particle generation from the dry etching process and a coating applied to at least a portion of the surface for rendering the surface less susceptible to chipping and/or particle generation, the coating comprising a silicon carbide coating
    Type: Application
    Filed: March 27, 2003
    Publication date: October 2, 2003
    Applicant: LSI Logic Corporation
    Inventor: Katsumi Aoki
  • Ball assignment for ball grid array package
    Publication number: 20030183419
    Abstract: A printed circuit board having contacts in a contact array of rows and columns. Groups of n columns of the contacts are electrically connected to n−1 columns of vias disposed interstitially in a via array between the n columns of the contacts. A major vertical routing channel is formed between adjacent groups of n columns of the contacts and the n−1 columns of vias. First electrical traces are electrically connected to a first number of the vias. The first electrical traces are routed to an outside edge of the via array through the major vertical routing channel.
    Type: Application
    Filed: June 2, 2003
    Publication date: October 2, 2003
    Applicant: LSI Logic Corporation
    Inventors: Leah M. Miller, Farshad Ghahghahi
  • Local interconnect
    Publication number: 20030186531
    Abstract: A method for forming the electrical interconnect levels and circuit elements of an integrated circuit is provided by the present invention. The method utilizes a relatively thin layer of conductive material having a higher resistance than the metal typically used to form electrical interconnections, such as titanium nitride, to provide relatively short local interconnections between circuit elements of the integrated circuit. In addition, this same thin layer of conductive material is used to form macro elements such as capacitors, resistors, and fuses in the integrated circuit. By allowing the removal of space consuming transverse electrical interconnect lines from the interconnect levels, the present invention increases the routing density of the electrical interconnect levels.
    Type: Application
    Filed: March 27, 2003
    Publication date: October 2, 2003
    Applicant: LSI Logic Corporation
    Inventors: Derryl D.J. Allman, James R. Hightower, Phonesavanh Saopraseuth
  • Low cost voltage controlled crystal oscillator (VCXO)
    Publication number: 20030184396
    Abstract: A circuit generally comprising a tank circuit and an inverter circuit. The tank circuit may be configured to generate a first signal having a frequency of oscillation in response to a second signal. The inverter circuit may be configured to (i) generate the second signal in response to inverting the first signal and (ii) adjust a delay in generating the second signal in response to an input signal to change the frequency of oscillation.
    Type: Application
    Filed: April 1, 2002
    Publication date: October 2, 2003
    Applicant: LSI LOGIC CORPORATION
    Inventors: Yoed I. Nehoran, Yuanping Zhao
  • Fast program to program verify method
    Publication number: 20030185053
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Application
    Filed: February 20, 2003
    Publication date: October 2, 2003
    Applicant: HALO LSI, INC.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Method of chemically altering a silicon surface and associated electrical devices
    Patent number: 6627556
    Abstract: A method of chemically altering a silicon surface and associated dielectric materials are disclosed.
    Type: Grant
    Filed: April 24, 2002
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Vladimir Zubkov
  • Integrated capacitor and fuse
    Patent number: 6627968
    Abstract: A process for forming a capacitive structure and a fuse structure in an integrated circuit device includes forming a first capacitor plate and first and second fuse electrodes in a first dielectric layer of the device. In a second dielectric layer overlying the first dielectric layer, a capacitor dielectric section overlying the first capacitor plate, and a fuse barrier section overlying and between the first and second fuse electrodes are formed simultaneously. In a conductive layer overlying the second dielectric layer, a second capacitor plate overlying the capacitor dielectric section, and a fuse overlying the fuse barrier section and contacting the first and second fuse electrodes are formed simultaneously. The capacitor dielectric section and the fuse barrier section may be defined simultaneously by selectively removing portions of the first dielectric layer during a single etching step.
    Type: Grant
    Filed: October 25, 2002
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Chuan-Cheng Cheng, Yauh-Ching Liu
  • Fast program to program verify method
    Patent number: 6628546
    Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.
    Type: Grant
    Filed: February 20, 2003
    Date of Patent: September 30, 2003
    Assignee: Halo LSI, Inc.
    Inventors: Seiki Ogura, Tomoko Ogura, Nori Ogura
  • Fibre Channel service parameter cache
    Patent number: 6629156
    Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to obtain a number of service parameters from a network device. The second circuit may be configured to store (i) a first portion of the service parameters in a first group comprising identification parameters, a number of pointers, and a control field and (ii) one or more second portions of the service parameters in one or more second groups, each comprising a communication parameter and a counter. Each of the number of pointers points to a null address or one of the one or more second groups.
    Type: Grant
    Filed: March 2, 2000
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Louis Odenwald, William Ortega
  • Method and apparatus for detecting backside contamination during fabrication of a semiconductor wafer
    Patent number: 6627466
    Abstract: A method of detecting contamination on a backside of a semiconductor wafer includes the steps of positioning the backside of the wafer in contact with a detection surface of a contaminant sensor, and detecting deformation of the detection surface of the contaminant sensor. The contaminant sensor may be incorporated into a fabrication device such as a wafer handling device, or can be utilized in the construction of a stand-alone device. An apparatus for detecting contamination on the backside of a semiconductor wafer is also disclosed.
    Type: Grant
    Filed: May 3, 2002
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventors: Michael J. Berman, George E. Bailey, Rennie G. Barber
  • Alternating shadow directories in pairs of storage spaces for data storage
    Patent number: 6629203
    Abstract: An improved shadow directory technique allocates storage space for directories in pairs in a logical volume. One of the spaces in each pair is used for a directory for locating data in the logical volume. The other space is reserved for an updated copy (shadow) of the directory if the directory is ever to be changed or updated. After the shadow directory is stored, it becomes a new directory for locating the data in place of the previous directory. The storage space containing the previous directory is unused, but retained as allocated for the next shadow directory, if needed. Since directory storage spaces are not deallocated, the improved shadow directory technique enables a simplified sequential-allocation storage management in a primarily data-add environment.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 30, 2003
    Assignee: LSI Logic Corporation
    Inventor: Donald R. Humlicek