Abstract: An improved shadow directory technique allocates storage space for directories in pairs in a logical volume. One of the spaces in each pair is used for a directory for locating data in the logical volume. The other space is reserved for an updated copy (shadow) of the directory if the directory is ever to be changed or updated. After the shadow directory is stored, it becomes a new directory for locating the data in place of the previous directory. The storage space containing the previous directory is unused, but retained as allocated for the next shadow directory, if needed. Since directory storage spaces are not deallocated, the improved shadow directory technique enables a simplified sequential-allocation storage management in a primarily data-add environment.

Abstract: A circuit comprising a memory, a queue, and a translator. The memory may be configured to store a message at an address at least as great as a base address. The queue may be configured to store a descriptor, wherein the descriptor is configured to have (i) an index, (ii) a routing field, and (iii) fewer bits than the address. The translator may be configured to translate between the address and the index.

Abstract: In the present invention a new method for program and program verify is described. The threshold voltage of the memory cell is shifted up and then measured with minimal charging and discharging of the bit lines and control gate lines. Bit line to control gate line capacitance is also used to reduce the number of voltage references needed. Program current is reduced by use of a load device coupled to the source diffusion. The result is increased program bandwidth with lower high voltage charge pump current consumption.

Abstract: Cell overlap is removed from rows during a cell placement procedure for an integrated circuit chip. The rows are partitioned into subrows so that cells in each subrow have a common characteristic vector. Cell overflow is removed from each of the subrows by moving a cell of an overflowed row or exchanging two cells, at least one of which is in the overflowed subrow. The half-cells of the dual height cells are moved to cell positions in a suitable pair of rows based on a calculated movement penalty. The movement is accomplished to align the half-cells and minimize the penalty. In preferred embodiments, the process is carried out by a computer under control of a computer program.

Abstract: A structure for programming a memory cell on an integrated circuit provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In an embodiment, the structure includes a conductive signal path extending through multiple horizontally conductive layers of the integrated circuit from a programming voltage pad (or node) to an input of the memory cell. The conductive signal path includes portions selected from multiple alternate path portions formed within the multiple horizontally conductive layers through which the signal path extends. An embodiment of a method for making a mask includes selecting one of multiple configurations of the programming structure portion to be formed using the mask. A computer-usable carrier medium may include digital representations of the alternative configurations for a programming structure portion from which a programming structure pattern may be selected.

Abstract: An integrated circuit device (10) comprises a semiconductor die (14) and an optical signal emitting diode (18) for communicating an optical signal, such as a clock or trigger signal, to individual circuits on the die (14). Each circuit includes a photosensitive active device implemented on the die for converting the received optical signal to an electronic signal for clocking or triggering a local circuit (e.g., a data storage register). Translucent material (20) encapsulates the emitter diode (18) and the die (14). The optically communicated signal has very low skew, which is independent of the topology of the die (14).

Abstract: A method and a means for determining an IDDQ test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die derived from the same lot of wafers as an integrated circuit. The method may further include setting the IDDQ test limit based upon the measured IDDQ value. In some embodiments, setting the IDDQ test limit may include correlating the IDDQ value of the test structure to calibration data. Accordingly, a means for conducting such a method may include one or more test structures formed upon a die and calibration data adapted to correlate a test structure IDDQ value to an IDDQ test limit of an integrated circuit. In some cases, the means for determining the IDDQ test limit may further include a means for increasing a substrate leakage current of the test structure.

Abstract: An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a first detection signal and a second detection signal in response to (i) an input signal, (ii) a first control signal, and (iii) a second control signal. The second circuit may be configured to generate a first output signal and a second output signal in response to (i) the first detection signal, (ii) the second detection signals, and (iii) a third control signal.

Abstract: An apparatus for constructing a number of integrated circuits from a single substrate is provided by the present invention. A number of integrated circuits are constructed on the single substrate. The individual integrated circuits are then separated by cutting the substrate with a dicing saw. A vacuum chuck is used to grasp the individual integrated circuits while a back grinding process is performed on the individual circuits to polish the circuits to a predetermined thickness. The integrated circuits are then placed into integrated circuit packages. By performing the back grinding process after the substrate has been divided into the separate individual circuits, the present invention eliminates the need to back grind portions of the substrate that are not further used, and tends to eliminate handling of the fragile thinned substrate.

Abstract: Clock cycle simulation involves modeling of clock cycles in a hardware module with a software model. Each simulated clock cycle involves several individual stages: Start, Execute, and End. During the start stage, output pin values for the model are calculated from an initial state of the module being simulated. Between the start stage and the execution stage, a combinatorial function of the modules outputs can be calculated. These calculated functions may be used as inputs to the modules in the execution stage. Afterwards, during the execute stage, input pin values are received by the model and the next state of the module is calculated based upon the current module state and the input pin values. Finally, during the last stage, i.e., the end stage, the internal state is updated; the internal state is defined as a set of the module's internal register and memory values.

Abstract: Relevant logic cells and waveforms of a circuit are automatically identified, traced and displayed by using conventional simulation, schematic viewing and waveform viewing tools. The input and output waveforms to and from each logic cell and a transition and a transition time point of each waveform are derived. The output waveform and a selected transition time point identify a predictive input waveform and its transition time, which cause the output signal transition at the selected transition time point. The predictive input signal is the output signal of a preceding, predictive logic cell, thereby identifying the preceding predictive logic cell. Repetitions of this procedure are performed with each new identified predictive logic cell to automatically derive a series or cone of logic cells which cause the desired output signal at a selected output signal transition time.

Abstract: A process for forming a capacitive structure that includes an upper layer having a first capacitor electrode section therein. A capacitor dielectric layer is formed adjacent the upper layer. The capacitor dielectric layer covers the first capacitor electrode section. A second capacitor electrode layer is formed adjacent the capacitor dielectric layer. The second capacitor electrode layer includes a second capacitor electrode section that at least partially covers the first capacitor electrode section, and which has an edge portion that extends beyond the underlying first capacitor electrode section. The capacitor dielectric layer being disposed between the first capacitor electrode section and the second capacitor electrode section. An upper dielectric layer is formed adjacent the second capacitor electrode section.

Abstract: A computer system incorporates bus snooping with a bus that does not enable bus snooping, such as the Advanced High-Performance Bus (AHB), to maintain cache coherency between caching devices and shared memory. Bus snooping capabilities are enabled by a stand-alone bus snooping device connected to the bus and the caching device or by bus snooping functions incorporated into the caching device. The bus snooping device monitors communications on the bus and causes invalidation of cached information to maintain cache coherency before the communications complete.

Abstract: An integrated circuit includes a substrate and a degenerated transistor. The degenerated transistor includes a control terminal formed on the substrate, a channel formed in the substrate beneath the first control terminal, first and second heavily-doped regions embedded in the substrate on opposing sides of the channel, first and second output contacts positioned on the first and second heavily-doped regions, respectively, and a lightly-doped region extending between the first heavily-doped region and the channel. The lightly-doped region has a length that is selected such that the first output contact is spaced from a respective edge of the control terminal by a distance that is at least twice as great as a minimum distance defined for the technology in which the integrated circuit is fabricated and the lightly-doped region has a desired resistance in series with the first output contact.

Abstract: In hardware multipliers, the generation of partial products is a necessary step in the process known to the art for efficient production of a final product. A way to increase the speed of hardware multipliers is through the use of the Booth algorithm. The alternate Booth partial product generation for hardware multipliers of the present invention is directed to a method and apparatus for eliminating the encoding of the bits of the multiplier prior to entering the partial product generating cell of the present invention which may result in less hardware and increased speed.

Abstract: An integrated circuit having input output buffers, where the integrated circuit is powered by at least a core power supply and an input output power supply. A level shifter receives an active low signal that indicates that the core power supply has powered down. The level shifter then outputs a known state upon receipt of the active low signal. A control circuit receives the known state form the level shifter, and then tristates the input output buffers upon receipt of the known state.

Abstract: Methods and associated structure for on the fly (dynamic) transition between versions among a management application process and an associated I/O subsystem. A management application program operable on a management system coupled to the I/O subsystem instantiates a script engine to execute script language commands for communicating with the I/O subsystem on behalf of the management application. The particular script engine instantiated is one that is compatible with the present revision of firmware operable in the I/O subsystem. When a script command execution causes a firmware upgrade in the I/O subsystem, the present script engine saves its state of operation, notifies the management application of the upgrade and resultant incompatibility and terminates. The management application then instantiates a new script engine compatible with the newly upgraded firmware version in the I/O subsystem.

Abstract: A dual-damascene process for forming an integrated circuit structure is described. The process includes forming a trench in a dielectric substrate, and forming a via mask layer over the dielectric substrate and the trench. An aperture is formed in the via mask layer overlying the trench, thereby exposing a portion of the underlying dielectric substrate. The exposed portion of the dielectric substrate is subjected to an ion beam to damage the exposed dielectric material. The damaged portion of the dielectric substrate is then removed, such as by etching, thereby forming a via cavity below the trench in the dielectric substrate. Generally, the damaged portion of the dielectric substrate etches at a faster rate than do adjacent non-damaged regions. With a faster etch, there is practically no outward spreading of the via cavity as the etch proceeds downward through the dielectric substrate, thereby forming a via cavity wall that is very nearly vertical.

Abstract: A resistor having a desired temperature coefficient of resistance and a total electrical resistance. A first resistor segment has a first temperature coefficient of resistance and a first electrical resistance. A second resistor segment has a second temperature coefficient of resistance and a second electrical resistance. The first resistor segment is electrically connected in series with the second resistor segment, and the total electrical resistance equals a sum of the first electrical resistance and the second electrical resistance. The desired temperature coefficient of resistance is determined at least in part by the first temperature coefficient of resistance and the first electrical resistance of the first resistor and the second temperature coefficient of resistance and the second electrical resistance of the second resistor.

Abstract: The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate.