Patents Assigned to LSI
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Patent number: 6545312Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: July 3, 2001Date of Patent: April 8, 2003Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6544854Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal.Type: GrantFiled: November 28, 2000Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Helmut Puchner, Gary K. Giust
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Patent number: 6546538Abstract: Provided is an integrated circuit (IC) device that includes a semiconductor substrate on which electronic components are formed and multiple metal layers on which wires are routed. Formed on the multiple metal layers is a capacitor that includes a first plate formed on a first metal layer and a second plate formed on a second metal layer that is adjacent to the first metal layer. An area in which the first plate and the second plate overlap has a width of at least twice the width of a typical wire on the IC device. Also provided is a technique for supplying power and ground to locations on an integrated circuit (IC) device that has multiple metal layers for routing wires and a substrate for forming electronic components. Initially, the technique identifies an overlap area where two of the multiple metal layers that are adjacent to each other have open space. A plate is then formed in the overlap area of each of the two metal layers so as to construct a capacitor.Type: GrantFiled: March 10, 2000Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Shalini Rubdi, Stefan Graef, Juergen Lahner
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Patent number: 6546541Abstract: A method and apparatus are provided for generating constraints for an integrated circuit logic re-synthesis algorithm. The method and apparatus receive a netlist of interconnected logic elements, which includes a plurality of nets, wherein each of the nets is coupled between a respective net driver logic element and at least one driven logic element. The method and apparatus also receive a maximum allowable input ramp time specification for the logic elements and an output ramp time specification for the net driver logic elements. A maximum interconnect capacitance constraint is then generated for each of the net driver logic elements based on the output ramp time specification for that net driver logic element and the maximum allowable input ramp time specification.Type: GrantFiled: February 20, 2001Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Dusan Petranovic, Ivan Pavisic, Aiguo Lu
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Patent number: 6546409Abstract: A digital processor and method for performing mathematical division in which performance degradation is mitigated by avoiding left shift and append (14) on the output of an ALU using pre-shift and append (18, 22) of the feedback from the quotient and remainder storage element (R, Q).Type: GrantFiled: June 9, 1999Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventor: Kar Lik Wong
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Patent number: 6544807Abstract: A process monitor includes a test circuit formed on a product die wherein the test circuit has a distribution of cell types that is substantially identical to that of the product die.Type: GrantFiled: November 3, 2000Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventor: Randall Bach
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Patent number: 6545305Abstract: A capacitor that is a metal to polysilicon capacitor. The capacitor is fabricated by forming a field oxide layer on a substrate. Then, a polysilicon segment is formed on the field oxide layer. This polysilicon segment forms a polysilicon bottom plate for the capacitor. A dielectric layer is formed and planarized. An opening is made in the dielectric layer to expose a portion of the polysilicon segment. Then, an oxide layer is formed on exposed portions of the polysilicon segment. A metal segment is formed on the oxide layer over the opening, wherein the metal segment forms a top-plate for the semiconductor device.Type: GrantFiled: April 14, 2000Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventor: Todd A. Randazzo
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Patent number: 6545288Abstract: A software tool and method for routing paths in a routing space. A grid is effectively built “on the fly”, therefore reducing the number of grid points which must be plotted. The boundaries of the routing space are defined. Blocks are then defined in the routing space. After the blocks have been defined, grid points are plotted corresponding to the corners of the blocks. The source points and target points are plotted, and grid points are plotted corresponding to the source and target points. Then, the paths from the source points to the target points are plotted along grid points which have been defined in the routing space. This process of defining the grid points not only reduces the size of data needed to describe the available routing space, but preferably obviates the need to run design rule checks.Type: GrantFiled: March 8, 2001Date of Patent: April 8, 2003Assignee: LSI Logic CorporationInventors: Radoslav Ratchkov, Anand Sethuraman
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Publication number: 20030064593Abstract: A method for creating a highly reflective surface on an electroplated conduction layer. A barrier layer is deposited on a substrate using a self ionized plasma deposition process. The barrier layer has a thickness of no more than about one hundred angstroms. An adhesion layer is deposited on the barrier layer, using a self ionized plasma deposition process. A seed layer is deposited on the adhesion layer, also using a self ionized plasma deposition process, at a bias of no les than about one hundred and fifty watts. The combination of the barrier layer, adhesion layer, and seed layer is at times referred to herein as the barrier seed layer. The conduction layer is electroplated on the seed layer, thereby forming the highly reflective surface on the conduction layer, where the highly reflective surface has a reflectance of greater than about seventy percent.Type: ApplicationFiled: October 10, 2002Publication date: April 3, 2003Applicant: LSI Logic CorporationInventors: Kiran Kumar, Zhihai Wang, Wilbur G. Catabay
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Publication number: 20030064588Abstract: A method of forming an electrically conductive interconnect on a substrate. An interconnection feature is formed on the substrate, and a first barrier layer is deposited on the substrate. The first barrier layer consists essentially of a diamond film. A seed layer consisting essentially of copper is deposited on the substrate, and a conductive layer consisting essentially of copper is deposited on the substrate. Thus, by using a diamond film as the barrier layer, diffusion of the copper from the conductive layer into the material of the substrate is substantially reduced and preferably eliminated.Type: ApplicationFiled: September 9, 2002Publication date: April 3, 2003Applicant: LSI Logic CorporationInventors: Wilbur G. Catabay, Zhihai Wang
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Patent number: 6543038Abstract: A method for calculating skew associated with providing a signal to a capacitive load along a first and second wire. The method includes steps of calculating a skew error which would result if the Elmore Model were used to calculate delays using the actual length of the wires, calculating a new effective length for the second wire based on the error which has been calculated, using the Elmore Model to calculate an effective delay which would be associated with providing the signal to the capacitive load along the new effective length of wire, and calculating skew using the effective delay which has been calculated. Preferably, the new effective length for the second wire is calculated by considering the actual lengths of the first and second wires, the capacitance of a unit length of wire and the capacitance of the capacitive load.Type: GrantFiled: January 26, 2001Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Alexander Tetelbaum
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Patent number: 6542460Abstract: In a multi-directional orthogonal frequency division modulation (OFDM) communication system, for example, on a digital subscriber line, an uplink channel is provided by a first group of the OFDM sub-channels (sub-carriers), and a downlink channel is provided by a second group of the OFDM sub-channels (sub-carriers). In one aspect, communication efficiency is improved by controlling the relative number of sub-channels allocated to each group, and hence controlling the capacity of the channels dynamically. Preferably, the relative capacities are controlled in response to demand for channel capacity. In another aspect, the orthogonality of the sub-carriers generated by different transmitters is improved by providing a frequency and/or time synchronising signal for providing reference frequency and timing.Type: GrantFiled: December 22, 1998Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Steven Richard Ring
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Patent number: 6543032Abstract: Provided are systems and techniques for optimizing an integrated circuit design, in which a critical zone is identified in an integrated circuit design and a plurality of alternative identities are applied in the critical zone in order to obtain a corresponding plurality of outcomes. Alternative representations are then identified as those of the plurality of outcomes pursuant to which at least one of ramptime and timing are improved, and a best one of the alternative representations is selected to replace into the critical zone based on specified priorities which include: (i) selecting based on reduction in ramptime violation; (ii) selecting from among alternative representations that preserve cell area based on timing improvement; and (iii) if all alternative representations increase cell area, selecting based on an evaluation of a relationship between timing decrement and area increment.Type: GrantFiled: October 2, 2000Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventors: Andrej A. Zolotykh, Elyar E. Gasanov, Alexander S. Podkolzin, Valery B. Kudryavtsev
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Patent number: 6541383Abstract: An arrangement for planarizing a surface of a semiconductor wafer. The arrangement includes a planarizing member having a planarizing surface configured to be (i) positioned in contact with and (ii) moved relative to the surface of the semiconductor wafer so as to remove material from the surface of the semiconductor wafer such that the surface of the semiconductor wafer is planarized. The arrangement also includes an adherence promoting ligand chemically bonded to the planarizing surface of the planarizing member. The arrangement further includes an abrasion particle chemically bonded to the adherence promoting ligand such that the abrasion particle is attached to the planarizing surface of the planarizing member. The arrangement also includes a conditioning bar having a conditioning portion positioned in contact with a wafer track defined on the planarizing member. The conditioning portion is configured so that the conditioning portion extends completely across the wafer track.Type: GrantFiled: June 29, 2000Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventors: Derryl D. J. Allman, John W. Gregory
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Patent number: 6542834Abstract: Methods for calculating a total capacitance of a metal wire in an integrated circuit is disclosed. In the present invention, a library containing predetermined wiring topologies is created. Each of the wiring topologies has an associated capacitive value. After extracting a layout topology of a segment of the metal wire, the layout topology is used to find and extract one of the predetermined wiring topologies in the library that corresponds to the layout topology. The associated capacitive value for the extracted wiring topology is used to calculate the total capacitance of the metal wire.Type: GrantFiled: November 24, 1999Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Charutosh Dixit
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Patent number: 6543026Abstract: Forward error correction apparatus and methods are described. A forward error correction method includes: (a) computing syndromes values; (b) computing an erasure location polynomial based upon one or more erasure locations; (c) computing modified syndromes based upon the computed erasure location polynomial and the computed syndrome values; (d) computing coefficients of an error location polynomial based upon the computed modified syndromes; (e) computing a composite error location polynomial based upon the computed coefficients of the error location polynomial; (f) computing a Chien polynomial based upon the computed composite error location polynomial; (g) performing a redundant Chien search on the computed composite error location polynomial to obtain error location values; and (h) evaluating the computed Chien polynomial based upon the error location values to obtain error and erasure values.Type: GrantFiled: September 10, 1999Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Tan C. Dadurian
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Patent number: 6542412Abstract: A fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables low voltage requirement on the floating gate during erase is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular to both the bit lines and control gate lines. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow erase access to the individual floating gate.Type: GrantFiled: January 28, 2002Date of Patent: April 1, 2003Assignee: Halo LSI, Inc.Inventors: Seiki Ogura, Tomoko Ogura
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Patent number: 6540467Abstract: A system and a method are provided for preventing damage to wafers arranged in a wafer cassette. In particular, an apparatus is provided to protect wafers arranged in a wafer cassette during insertion of a wafer into the cassette. In one embodiment, the apparatus may be a separate entity from the wafer cassette. In this manner, the apparatus may be situated about the cassette such that the wafers arranged in the cassette are protected during insertion of a wafer. In another embodiment, the wafer cassette itself may be adapted to partially cover and protect the wafers arranged in the cassette during insertion of a wafer. Consequently, a method is provided using either embodiment of the apparatus. In particular, the method may include inserting a wafer into a wafer cassette by shielding one or more slots of the cassette, exposing a designated slot of the cassette, and inserting a wafer into the designated slot.Type: GrantFiled: June 18, 2001Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventors: Nael O. Zohni, Clifford Fishley
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Patent number: 6542196Abstract: A method for de-interlacing a decoded video stream comprising the steps of (A) defining a sampling period, (B) sampling the decoded video stream during the sampling period to define one or more parameters, (C) adjusting a threshold and a level of the decoded video stream used in processing, in response to the one or more parameters, (D) filtering the decoded video stream using a filter tool selected from a plurality of filters, in response to the one or more parameters.Type: GrantFiled: November 5, 1999Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Daniel Watkins
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Patent number: 6542434Abstract: A programmable self time circuit for controlling bit line separation in a memory includes multiple self time word lines, each of which is connected to at least one core cell of the memory for activating the cell. The self time word lines have enable signals that can either be programmed on/off, or can be externally controlled for variation of the amount of bit line separation developed during a memory access.Type: GrantFiled: May 31, 2001Date of Patent: April 1, 2003Assignee: LSI Logic CorporationInventor: Carl A. Monzel