Abstract: A recursive decoder for decoding a binary codeword of length N having a first stage, at least one intermediate stage, and a final stage. The first stage including a plurality of decoder groups, each of the groups having a plurality of sets of first and second decoders, each of the first and second decoders having a plurality of inputs and an output, a plurality of adder groups, each of the adders having a first input connected to the output of the first decoder of one of the sets and a second input connected to the output of the second decoder of one of the sets, and an output.

Abstract: A multiple channel communication system includes a plurality of network communication ports, a plurality of communication devices and an autonegotiation controller. Each communication device is coupled to a respective one of the plurality of network communication ports. The autonegotiation controller is coupled to and shared by the plurality of communication devices.

Abstract: A test transistor structure formed in a semiconductor device has a thick-oxide transistor with an elongated serpentine-shaped metal gate. The gate is used to first measure the threshold voltage of the thick-oxide test structure. Then, a current is passed through the elongated metal line which forms the serpentine gate to heat the area of the test structure. While being heated, a stress voltage is applied between the substrate and one end of the gate electrode, this stress voltage being much larger than the logic voltage used in operating thin-oxide transistors on the chip. After a selected time, the current is removed, the stress voltage is removed, and the threshold voltage of the thick-oxide transistor is again measured and compared to the original value. Any reduction in threshold voltage can be attributed to the migration of positive charge to the silicon-to-oxide interface beneath the gate, and is proportional to the area between the source and drain regions of the test transistor.

Abstract: Damaged surfaces of a low k carbon-containing silicon oxide dielectric material are treated with one or more carbon-containing gases, and in the absence of an oxidizing agent, to inhibit subsequent formation of silicon-hydroxyl bonds when the damaged surfaces of the low k dielectric material are thereafter exposed to moisture. The carbon-containing gas treatment of the invention is carried out after the step of oxidizing or “ashing” the resist mask to remove the mask, but prior to exposure of the damaged surfaces of the low k dielectric material to moisture. Optionally, the carbon-containing gas treatment may also be carried out after the initial step of etching the low k carbon-containing silicon oxide dielectric material to form vias or contact openings as well, particularly when exposure of the damaged surfaces of the low k dielectric material to moisture after the via etching step and prior to the resist removing oxidation step is possible.

Abstract: An integrated circuit includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid electrically coupled to the plurality of circuits. The power bus grid is formed of a plurality of power bus straps having a strap density that progressively varies with distance from the geometric center toward the periphery.

Abstract: A film of low k dielectric material formed on a semiconductor substrate is treated to inhibit cracking of the film of low k dielectric material during subsequent exposure of the film of low k dielectric material to elevated temperatures by implanting the film of low k dielectric material with hydrogen ions by applying a negative DC bias to the semiconductor substrate in the presence of a plasma of hydrogen ions. The semiconductor substrate is mounted on an electrically conductive substrate support in a reactor and the negative DC bias is applied to the semiconductor substrate by connecting the electrically conductive substrate support to a source of negative DC bias while hydrogen ions are generated by the plasma in the reactor to thereby cause the hydrogen ions to implant into the film of low k dielectric material on the semiconductor substrate.

Abstract: A system for precisely locating an absolute position of a target structure disposed at a known relative position on a substrate, where the substrate has devices in a pattern. Input means receive information, including a substrate size, a pattern offset, a device size, the known relative position of the target structure, and a target structure shape. Staging means receive the substrate in a known orientation. Processing means are used to locate several positions. A center position of the substrate is located from the substrate size and the known orientation of the substrate. A first intermediate position is located by combining the center position of the substrate with the pattern offset. A second intermediate position is located by combining the first intermediate position with at least a first component of the device size. A third intermediate position is located by combining the second intermediate position with the known relative position of the target structure.

Abstract: An electrical cable suitable for transmission of data signals cable includes a dual layer ribbon cable with a first layer being offset from the other layer by an offset distance. The dual layer ribbon construction of the cable allows the cable to be compliant with a SCSI standard and to include a VHDCI compliant connector. The cable may have a first Z form where a spacer connects an insulator in the first layer with an insulator in the second layer, a second form in which an insulator of the first layer is attached to an insulator in the second layer, or a modified second form in which a spacer is attached between adjacent insulators in the same layer. The double layer ribbon cable construction allows the width of the cable to be reduced to accommodate a smaller pitched, larger pin number VHDCI compliant connector anywhere along the length of the cable.

Abstract: Fabricated using a complementary metal oxide semiconductor process including the use of salicides, an input and power protection circuit for use in an integrated circuit protects voltage and signal terminals from both overvoltage and ESD pulses. A diode connected is connected between a first terminal and an inter-transistor node, a field effect transistor is connected between the inter-transistor node and a second terminal, and a lateral bipolar transistor, with a base connected to the inter-transistor node, is connected between the first and the second terminals. When an ESD pulse appears on the first terminal, the voltage at the inter-transistor node increases until a snapback trigger voltage of the field effect transistor is reached whereupon current flows from the first terminal, through the emitter-base junction of the lateral bipolar transistor, through the inter-transistor node, through the field effect transistor, and to the second terminal.

Abstract: A network comprises at least one host processing system, a number of storage controllers, each coupled to one of a plurality of storage arrays, each storage array including at least one mass storage device. Each storage controller may be couple to at least one host processing system and to at least one other storage controller to control access of the host processing systems to the mass storage devices. Multiple copies of data are maintained in storage arrays that are geographically remote to each other, such that any copy can be accessed by any host. Each storage controller includes an interface with a host that emulates a mass storage device and an interface with a local storage array that emulates a host. The interfaces to the host and local storage arrays are independent of the type of host or devices in the local storage array. Two or more hosts may be dissimilar to each other, and two or more storage arrays may include dissimilar mass storage devices. Hosts access stored data using virtual addressing.

Abstract: An apparatus detects the approach and touch-down of an object relative to a sensor panel. The apparatus includes a digital filter for determining a first derivative of a current flow in the sensor panel and a controller determines when the first derivative reaches a maximum. In a preferred embodiment, a magnitude for current flow in a plurality of corners of the sensor panel is determined by the controller. These magnitudes are then summed to determine a current flow from which the first derivative is computed. The current flow is analyzed by the controller to determine when an object is approaching the sensor panel, has contacted the sensor panel, and is withdrawn from the sensor panel. Thresholds are used to avoid false detection of approaching objects.

Abstract: A practical approach for synthesis for million gate ASICs is based on the use of synthesis shells. The synthesis shell is generated by beginning with a gate level description of a fully characterized and optimized block. This gate level description is reduced by removing internal gates to produce a synthesis shell of the synthesized block. The synthesis shell preserves input load and fanout for the block, output delay relative to clock for the block, setup/hold constraints on input signals relative to the clock for the block, and delay from input to output for pass through signals for the block. Such a synthesis shell can be used as a substitute for original design netlists and can be used for hierarchical synthesis in a customer's design environment, or as a deliverable from a provider of ASIC services in order to protect the intellectual property of such a provider.

Abstract: Provided is a technique for forming an indium field implant at the bottom of an STI trench to strengthen the p-well under field oxide, but to not weaken the n-well under the field oxide. The diffusivity of indium is an order of magnitude smaller than that of boron and the activation level of indium is high enough for well dopings. Thus, the implanted indium is able to keep the concentration of p-dopant at the p-n well junction under the field isolation and the oxide/silicon interface high, even with boron depletion, so that punchthrough is avoided.

Abstract: The present invention includes a pad driver circuit that has a driver, a power-on circuit coupled to the driver and a power-off circuit coupled to the driver. The power-on circuit is coupled to a pad via the power-off circuit. The power-on circuit provides a high impedance path between the pad and a power supply, particularly when the power supply is off. The power-off circuit provides a stepped-down voltage to the driver when the voltage signal is received. The driver is an open drain driver that includes series pull-down devices. The pad driver further includes a second power off circuit coupled to the driver. The power-on circuit provides a power supply voltage to the driver when a power supply is on. The power-on device preferably includes an inverter coupled to receive a power supply voltage and a clamp coupled to receive an output of the inverter wherein the clamp provides a voltage responsive to the power supply voltage.

Abstract: A metal-insulator-metal capacitor is formed between interconnect layers of an integrated circuit with one of the plates of the capacitor formed integrally with one of the interconnect layers. A dielectric layer is formed on top of the interconnect layer, and a top capacitor plate is formed thereon. A bottom plate is defined by the interconnect layer and extends laterally beyond the top plate so that via interconnects may connect to both plates. An intermetal dielectric (IMD) layer separates the interconnect layer and the capacitor from the next interconnect layer above, and the via interconnects are formed through the IMD layer to connect the above interconnect layer to the capacitor plates. The dielectric layer on top of the interconnect layer that defines the bottom plate and another dielectric layer formed on top of the top plate may serve as etch stops for forming the vias for the via interconnects to different levels.

Abstract: A detector of an oscillation stopping, which detects the stopping of the oscillation of external clock 11, without increasing the load of CPU 45 in the micro computer 40, and generates a signal to reset the micro computer or exchanges the system clock from the external clock to an inner clock. In an embodiment, one shot pulse is generated for every standing up and/or down edge of the external clock. A capacitor of the charge-discharge circuit is charged and discharged at every one shot pulse. The voltage of the charge-discharge circuit is watched by a Schmitt circuit. When the voltage of the charge-discharge circuit exceeds a predetermined voltage, a signal for resetting the micro computer is generated. In another embodiment, an inner clock oscillation circuit, comprised of a ring oscillator, for example, is actuated, when the voltage of the charge/discharge circuit exceeds a predetermined voltage, and the system clock of the micro computer is exchanged to the inner clock from the external clock.

Abstract: In the present invention a nonvolatile memory array architecture can be realized by a fabrication process more compatible to an MOS logic fabrication process as compared with previous nonvolatile memory array architectures. Higher write and/or read speed is possible because of a lower bit line resistance. A high hard bit density near 4F2 is possible when a self-align contact technology and a border less contact technology are used. Connection regions are formed throughout the memory array comprising four cells that are connected to one bit line. The connection regions can be formed in the same processing step with opposite conductivity regions for economy of processing. A plurality of memory cells are two dimensionally disposed in two different directions with connection regions, conductive bit lines extending in the first direction, conductive word lines extending in the second direction, and conductive control lines.

Abstract: A method for chemical-mechanical polishing of a layer that is deposited on a surface of an integrated circuit substrate is described. The method includes: (1) immobilizing the integrated circuit substrate using a substrate holder such that the integrated circuit substrate surface is positioned against a surface of a polishing pad, which is mounted on a supporting surface; (2) a first stage of polishing the substrate surface including maintaining a predetermined difference between the rotational velocity of the polishing pad and the rotational velocity of the substrate holder allowing an endpoint of the chemical-mechanical polishing process of the layer to be detected; and (3) a second stage of polishing the substrate such that the rotational velocity of the polishing pad and the rotational velocity of the substrate holder are substantially the same to produce a substantially planar substrate surface.

Abstract: A multiprocessor data processing system for handling a plurality of queues within the data processing system. Each queue is associated with a pointer. A first queue is designated as the current queue along with a first pointer associated with the first queue. This first pointer is designated as a current pointer. Entries are read within the current queue using the current pointer. In response to a condition requiring a change in queues, the current pointer is stored and another pointer is designated or loaded for use as the current pointer. Entries are read with the new current pointer within a queue associated with that pointer.

Abstract: The present invention is directed to an electrical cable. An electrical cable may include a first flat conductor surrounded by an insulator and a second flat conductor surrounded by an insulator, wherein the first flat conductor and the second flat conductor are spaced so as to form an electrical differential pair.