Abstract: The present invention is directed to an electrical cable. An electrical cable may include a first flat conductor surrounded by an insulator and a second flat conductor surrounded by an insulator, wherein the first flat conductor and the second flat conductor are spaced so as to form an electrical differential pair.

Abstract: A state machine is disclosed that is capable of providing improved performance as realized in a hardware embodiment while providing the flexibility of a software implemented state machine. The state machine is first implemented in software, and then is realized in a hardware embodiment based upon the software implemented state machine. Flexibility is added to the hardware realized state machine by providing registers for the hardware embodiment so that the register corresponds to states of the software implementation. As a result, at least one aspect of the hardware realized state machine may be modified without requiring redesigning the configuration of the hardware embodiment.

Abstract: A microprocessor system includes a core CPU for instruction execution and a coprocessor interconnected with said core CPU for system control and exception processing. The coprocessor includes a plurality of exception handling registers including an exception program counter having a restart location stored therein for use after an exception is serviced, a status register having operating mode identification and interrupt enabling bits, and a configuration and cache control register. Interrupt processing is compatible with a plurality of instruction sets with a particular instruction set being designated by setting at least one bit in the configuration and cache control register. Registers are provided to save the operating state of the CPU prior to interrupt enable, the operating state of the CPU being restored after exception processing is completed and user mode is reestablished.

Abstract: An apparatus comprising a drive server, a control server and one or more decoder devices. The drive server may be configured to present one or more compressed data streams in response to one or more first control signals. The control server may be configured to present one or more of the compressed data streams in response to (i) one or more request signals and (ii) the one or more compressed data streams. The decoder devices may be configured to present a decoded video signal and a decoded audio signal in response to (i) one or more second control signals and (ii) the one or more compressed data streams. The navigation software, which traditionally is processed local to the decoder, may be processed on the control server. The control server may be enabled to control the remote decoder.

Abstract: A system and method are presented for incorporating boundary scan test capability in an embedded memory. Existing half-latches within the memory are augmented to create full-latches, configurable as a scan register. This requires substantially less circuitry than if the entire scan register was created separately. Furthermore, separate signal paths are maintained for the functional signals and for the boundary scan data. Therefore, the boundary scan logic does not contribute additional propagation delay to the functional signals. Also, because the test circuitry is within the memory (rather than external to it), placing and routing of the scan circuitry is much less complicated than with previous methods.

Abstract: A serial data transceiver is presented which includes elements which facilitate testing using only the serial data transfer terminals of the transceiver. The serial data transceiver includes a transmitter and a receiver. The transmitter receives parallel data, converts the parallel data to a serial data stream, and transmits the serial data stream. The receiver receives a serial data stream, converts the serial data stream to parallel data, and provides the parallel data. During testing, parallel data produced by the receiver is routed to the transmitter input. In one embodiment, the transmitter includes a first router for routing parallel input data to the transmitter, and the receiver includes a second router for routing parallel output data produced by the receiver. The first router is coupled to the second router, both routers receive a test signal.

Abstract: A memory buffer allowing preliminary access to an upstream data portion in a data stream and a method for allowing the access. This memory buffer is a “peek-ahead” FIFO comprising a data input that receives a data stream, a data output, a circular FIFO buffer that stores data from the input at a circulating read location and provided data from a circulating write location to the data output. The memory buffer also has read and write pointers that indicate the read and write locations in the FIFO buffer. If the upstream data portion is stored in the memory buffer, the read pointer can temporarily advance by an offset number of memory locations to allow reading of the upstream data portion. In one embodiment, this memory buffer is included in a DVD decoder and is used to identify the type of an incoming packet before the entire header of the packet is processed. Also described is a method and system for parsing data words from an interleaved byte stream.

Abstract: A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop, such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals.

Abstract: Upon receiving a normal select signal to switch from one clock to another the first clock continues as the output for a number of clock periods. The normal select signal is treated as a disconnect control signal only at the next positive edge of the first clock. The disconnect signal is delayed for a number of cycles and then applied to the control gate of the first clock only when a negative edge of the first clock is detected. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output. The connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected causing the second clock to disconnect from the output only at a negative edge.

Abstract: A capacitor has a pair of plates separated by a capacitor dielectric material which is formed of multiple separate layers of different dielectric materials having different electrical characteristics. The different electrical characteristics are represented by linearity curves that curve relatively oppositely with respect to one another. Combining the different dielectric materials and separate layers achieves selected electrical characteristics from the overall capacitor dielectric material. The capacitor dielectric material may be formed with a top layer, a middle layer and a bottom layer. The middle layer may be formed of relatively high leakage dielectric and/or relatively high dielectric constant material, and the top and bottom layers may be formed of barrier material which is substantially resistant to leakage current and which exhibits a relatively lower dielectric constant.

Abstract: An audio system that automatically corrects for variations in spectral balance in audio source material. The audio system comprises a power spectrum analyzer and a source correction equalizer unit coupled to receive an audio input signal, and an index control unit coupled to a spectral balance correction data memory. A reference spectral balance may initially be established by playing a reference source medium with desired sound attributes. The power spectrum analyzer characterizes the spectral balance of the reference source medium, storing the results in non-volatile memory. When a particular source medium is played for the first time, the index control unit reads an identifying parameter from the particular source medium. Because there is no entry for the identifying parameter in spectral balance correction data memory, the particular source medium has not been previously played on the audio system.

Abstract: A circuit simulating apparatus includes a netlist extracting unit extracting a netlist from circuit diagram data, an unnecessary circuit disconnecting unit forming a netlist with an unnecessary circuit disconnected, from the netlist extracted by the netlist extracting unit, based on an unnecessary circuit disconnecting terminal designated by an unnecessary circuit disconnecting terminal designating unit, and a circuit simulation unit performing a circuit simulation using a simulation input file formed by using the netlist with the unnecessary circuit disconnected. As the circuit simulation is performed using the simulation input file formed from the netlist with the unnecessary circuit disconnected, the time necessary for the circuit simulation can be reduced.

Abstract: An optical-disk play-back system has a lens that receives a light beam reflected from a data surface of an optical disk. The lens focuses the light on four quadrant photodiodes. The position of the lens relative to the photodiodes is adjusted by a standard tracking control loop. In addition, the sledge position is controlled by a sledge-center-error signal. Since the sledge position changes only infrequently, the center error is a low-frequency signal. A non-linear center-error-generating circuit uses two op-amp stages. Signals from an inner pair of photodiodes are summed and applied to one input of the first-stage op amp, while signals from an outer pair of photodiodes are summed and applied to the other input of the first-stage op amp. The first-stage op amp output an overall error signal that includes high-frequency errors. A high-pass filter removes low-frequency components output from the first-stage op amp. The high-pass filter drives an inverting input of the second-stage op amp.

Abstract: An improvement to a process for manufacturing complementary metal oxide semiconductor devices on a monolithic substrate, where the improved process forms nonvolatile memory devices and programmable logic devices. The improvement includes exposing gate electrodes of a selected portion of the complementary metal oxide semiconductor devices at a point in the process where the gate electrodes have been previously covered by a protective material layer. A capacitive material layer is deposited on the monolithic substrate, such that it contacts the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices. A top electrode material layer is deposited on the monolithic substrate, such that the top electrode material layer contacts the capacitive material layer in a region overlying the exposed gate electrodes of the selected portion of the complementary metal oxide semiconductor devices.

Abstract: A method and apparatus for optimizing crossover voltage for differential pair switches in a current-steering digital-to-analog converter or the like are disclosed. An array of at least one or more MOSFET switches may be utilized to control the crossover voltage of a differential pair of transistors such that the off time overlap of the differential pair transistors is optimized. In one embodiment, the pull-up and pull-down times of the input for the differential pair transistors are optimized such that the differential pair transistors are not turned off simultaneously. The array of switches may be n-channel MOSFETs when the differential pair are p-channel MOSFETs. Likewise, the array of switches may be p-channel MOSFETs when the differential pair are n-channel MOSFETs. The output of the diflerential pair is free of crossover glitches and is capable of being utilized in a data converter such as a current-steering digital-to-analog converter (DAC).

Abstract: A battery charging circuit for portable electronic devices including a photovoltaic cell for generating electrical current for charging of batteries. The charging circuit includes a state machine charge control circuit to selectively apply the electrical current generated by the photovoltaic cell to the batteries for charging and/or to the operational circuits of the portable electronic device for operation of the device. The photovoltaic cell, charge control circuit and operational circuits may be packaged in a number of alternative embodiments. In a first embodiment the photovoltaic cell and charge control circuit are integrated in a single circuit package. In a second, the various components are in separate circuit packages to enhance flexibility in design options. In a third embodiment, the charge control circuit is integrated with the operational circuits of the device.

Abstract: A method of analyzing ADCs, comprising providing a test waveform, sampling the test waveform in an ADC at a frequency different from the test waveform, providing the output samples of the ADC to a logic analyzer means, storing the output samples over a predetermined time interval in memory in the logic analyzer means, and providing from the stored samples, a graphical visual representation of the sampled test waveform.

Abstract: Routing of electrical connections between cells arranged in cell columns on an integrated circuit (IC) die. Electrical connections are routed on a routing layer between cells located in a first cell column. An identification is made of an available off-grid resource capable of being used for wire routing that is both within the first cell column and on the routing layer. An electrical connection is routed between a first cell and a second cell located in different cell columns using at least a portion of the identified available off-grid resource. Also, an integrated circuit die which includes vertical power rails and vertical ground rails. Cell columns, including a first cell column and a second cell column, are each bordered by a vertical power rail and a vertical ground rail. A channel is provided between the first cell column and the second cell column.

Abstract: A graphical video editing system that allows manipulation of images for input to the video encoding and decoding process. The debugging of video encoders and decoders is aided by user controlled editing of problem areas in test images, and the graphical video editing system is coupled directly to the video encoder or decoder being debugged so that the effects of the editing can be immediately observed. This system advantageously provides a speedup in the debugging process by simplifying the detection of problem areas and providing a fast method for narrowing the possible causes of image flaws. Broadly speaking, the present invention contemplates a graphical video editing system for regeneration of bitstreams. The system comprises an encoder module, a decoder module, a display editor module and a display. The encoder module is configured to receive an input image and to convert the input image into an encoded bitstream.

Abstract: The present invention provides a portable computers capable of facilitating management of actual photo-image in association with each other, thereby remarkably expanding the application range of the actual phot-image data. The portable computer is connectable directly or through a memory medium to the main computer in a fixed base. The portable computer comprises: a digital camera detachably provided for successively taking actual photo-images; position specifying identification data setting means for setting identification data to specify at least one of photographing related positions consisting of a position of an object for photography taken by said digital camera and a position where photography was taken by said digital camera; and actual photo-image data memory means for storing the identification data set by said position specifying identification data setting means in association with actual photo-image data outputted from the digital camera.