Abstract: Water for use in wet oxidation of semiconductor surfaces may be generated by reacting ultra pure hydrogen and ultra pure gaseous oxygen without a flame. Because no flame is used, contamination due to a flame impinging on components of a “torch” is not a problem. Flame-free generation of water is accomplished by reacting hydrogen and oxygen under conditions that do not result in ignition. This may be accomplished by provided a diluted hydrogen stream in which molecular hydrogen is mixed with a diluent such as a noble gas or nitrogen. This use of diluted hydrogen also reduces or eliminates the danger of explosion. This can simplify the apparatus design by eliminating the need for complicated interlocks, flame detectors, etc.

Abstract: The present invention describes an interposer which improves the thermal performance of a semiconductor device. The interposer may be situated between a substrate and a board. The interposer is attached to two layers of solder balls. The first layer of solder balls electrically and mechanically connects the interposer to the substrate. The second layer of solder balls electrically and mechanically connects the interposer to the board. In one aspect, the coefficient of thermal expansion (CTE) of the interposer may be flexibly selected to reduce thermal strain-induced stress for either or both layers of solder balls resulting from thermal performance differences between the substrate and the interposer or the interposer and the board. In another aspect, the CTE of the interposer may be reduced to allow a lower CTE for the substrate, which in turn may reduce thermal strain-induced stress for solder balls between the substrate and a die attached to the substrate.

Abstract: The present invention includes a Command Queuing Engine (CQE) that is a firmware-assist block which processes some of the firmware tasks related to command and context management preferably for SCSI. When enabled, CQE will decode SCSI commands as they arrive, and determine if DMA contexts can be automatically configured and started to transfer the data for those commands. CQE can also program DMA contexts to automatically return status information either after the disk has completed a transfer (as in non-cached writes) or after the DMA transfer is completed (as in reads or cached writes). CQE also utilizes a buffer-based linked-list to queue the SCSI commands as they arrive for future DMA context configuration. The present invention provides automated recognition and linking of commands belonging to a common thread, i.e., are sequential. The present invention also provides extensive thread boundary information and flexible firmware control for reordering commands.

Abstract: A compensation capacitance is utilized in a multiport memory device to compensate for the effect of bit line coupling capacitance. A first compensation capacitance is applied between a read bit line and a write bar bit line, and a second compensation capacitance is applied between a write bit line and a read bar bit line to compensate for the effect of bit line capacitance that adversely affects the differential voltage swing at a the read bit line. In one embodiment, the compensation capacitances are equal to the value of the compensation capacitances. In an alternative embodiment, each compensation capacitance comprises two compensation capacitors additively combined in parallel each having a value of one-half of the coupling capacitance. The compensation capacitance may be variable so that compensation of the coupling capacitance may be optimized after fabrication of the integrated circuit.

Abstract: An automatic input threshold selector includes a maximum value level decision circuit, and an input threshold setting circuit. The maximum value level decision circuit decides, among m+1 level layers defined by m maximum value decision levels, a level layer to which the maximum value of an input signal belongs. The input threshold setting circuit sets an input threshold by selecting one of n input threshold candidates in response to the level layer to which the input signal maximum value belongs. These circuits are implemented as a simple combination of a voltage comparator, logic gates and the like. This makes it possible to solve a problem of a conventional automatic input threshold selector in that its circuit scale and power consumption is rather large because it includes a peak-hold circuit and a bottom-hold circuit.

Abstract: An apparatus performs motion estimation based on a reference image and a target image. The apparatus has a command memory for storing a motion estimation command list segment and a search engine connected to the command memory. The search engine retrieves and processes the command list segment stored in the memory. The search engine in turn has a reference window memory containing one or more reference data segments, a target memory containing one or more target data segments, and a data path engine for generating a score for each offset between data in the reference window memory and data stored in the target memory. A result memory receives outputs from the motion estimation search engine in the form of motion estimation result list segments. The reference window memory, target memory, and result memory may be double-buffered to minimize system memory latencies. Moreover, target and reference fetches may be shared by up to four search targets in a split search command.

Abstract: An ASIC design methodology in which portions of the ASIC are implemented in silicon or other suitable semiconductor technology at an early stage in the design flow through the use of a series of interim devices. The invention provides a method in which additional portions or subsystems of the integrated circuit are incorporated into successive versions of the interim device. In this manner, the invention provides for the gradual incorporation of a plurality of architectural subsystems into the integrated device such that the synthesis and verification of each iteration is broken into manageable pieces. In the preferred embodiment, this design method is facilitated by incorporating a programmable portion into the design flow of each interim device such that each interim device includes a custom portion into which the subsystems that have been implemented in silicon are fabricated and a programmable portion.

Abstract: A method and apparatus for increasing performance in a data processing system. The data processing system includes a plurality of storage devices and a backup storage device. The backup storage device is configured as a log device. Data is logged to the backup storage device after the backup storage device has been configured as a log device. In response to a failure of a storage device within the plurality of storage devices, the backup storage device is reconfigured to be used as a replacement for the failed storage device.

Abstract: A multimedia decoder is provided that inserts synchronization words into elementary linear pulse-code modulation (LPCM) audio bitstreams. In one embodiment, the multimedia decoder includes a pre-parser, a memory, and an audio decoder module. The pre-parser receives a multimedia bitstream and separates it into an audio substream and a video substream, and inserts a synchronization words before each data packet in the audio substream while forming it into an elementary bitstream. The memory is coupled to the pre-parser to buffer the elementary audio bitstream, and the audio decoder module is coupled to the memory to retrieve the elementary audio bitstream and convert it into a digital audio signal. The inserted synchronization word may comprise between from four to ten bytes in length. In one particular implementation, the inserted synchronization word includes the ASCII representation of the letters LSILOGIC.

Abstract: A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.

Abstract: A process is described for using a silicon layer as an implant and out-diffusion layer, for forming defect-free source/drain regions in a semiconductor substrate, and also for subsequent formation of silicon nitride spacers. A nitrogen-containing dopant barrier layer is first formed over a single crystal semiconductor substrate by nitridating either a previously formed gate oxide layer, or a silicon layer formed over the gate oxide layer, to form a barrier layer comprising either a silicon, oxygen, and nitrogen compound or a compound of silicon and nitrogen. The nitridating may be carried out using a nitrogen plasma followed by an anneal. A polysilicon gate electrode is then formed over this barrier layer, and the exposed portions of the barrier layer remaining are removed. An amorphous silicon layer of predetermined thickness is then formed over the substrate and polysilicon gate electrode.

Abstract: A serial data transceiver architecture and test method are presented for measuring the amount of jitter within a serial data stream. A transmitter of the transceiver receives parallel input data at a transmit data input port, converts the parallel input data to a serial data stream having data windows separated by data transition periods, and produces the serial data stream at a transmitter output port. A receiver of the transceiver receives a serial data stream at a receiver input port, converts the serial data stream to parallel output data, and provides the parallel output data at a receive data output port.

Abstract: An algorithm based on motion compensation uses a temporal support of five fields of video to produce a progressive frame. The moving average of the motion compensated field lines temporally adjacent to the field to be de-interlaced are used, after a non-linear filtering, as the missing lines to complete the progressive video frame.

Abstract: A disk mirroring method operable in a disk array storage system for storing N images of a block of data across M drives (N>=3 and M>=N) to enhance flexibility in configuration of mirrored and non-mirrored LUNs. Each of the N copies of data resides on a different drive such that if N−1 drives fail, the original block of data is recoverable. Data blocks may be striped or non-striped over the plurality of drives. Where the data is striped, each segment of the stripe has at least two mirrored images on other drives of the array. The present invention therefore enhances configuration flexibility as compared to prior techniques because all drives of the array may be used for mirrored copies regardless of the number of drives. The present invention therefore does not waste space where, for example, an odd number of drives are configured in the LUN.

Abstract: A system for coupling a ball fitting connected to a first tubing to a socket fitting connected to a second tubing. A first coupling forms an aperture having a diameter that is larger than the diameter of the ball fitting, and receives the ball fitting. The first coupling forms an annular race, with an annular surface disposed between the annular race and the aperture. First split ring pieces are assembled into a first ring that forms an aperture having a diameter that is smaller than the diameter of the ball fitting, and receives the first tubing. The first ring forms an annular ridge that engages the annular race, and aligns the first split ring pieces. The annular surface applies uniform axial pressure to a first surface of the first ring. The first ring has a second surface opposing the first surface that applies uniform axial pressure to a back portion of the ball fitting.

Abstract: One or more improved transmit units tightly integrated into an enhanced cluster cache with controller. Coherent memory transactions in a loosely coupled computer network are supported by sending all cache updates to all computers in the loosely coupled computer network through high speed, low latency and high bandwidth serial lines linking all computers to all other computers. The cluster cache controller may include a local cache controller and/or as a local bus controller. The local bus controller is operable to coupled the cluster cache to an I/O subsystem. A local cache memory preferably caches data and/or instructions, or locations thereof for the entire computer, making the local computer cache available to the entire computer cluster through the transmit unit. Each transfer unit is a full-duplex transceiver that includes transmitter and receiver functions. Each transfer unit can send and receive data simultaneously since operation of their transmitter and receiver functions are independent.

Abstract: A method of forming a low loop height wire interconnection in a semiconductor package including a die having a multiple row bond pad layout, and a wire bonded electrical interconnection formed using the method consists of the steps: forming a first ball bond from a first wire at a first bonding location; looping the first wire to a first bond pad of a die; forming a first stitch bond between the first wire and the first bond pad; forming a second ball bond from a second wire at a second bond pad of the die; looping the second wire to a second bonding location, wherein the second wire does not contact the first wire; and forming a second stitch bond between the second wire and the second bonding location.

Abstract: An apparatus for determining temperature of a semiconductor wafer during wafer fabrication is disclosed. The semiconductor wafer has a response circuit. The apparatus includes a signal transceiver for (i) transmitting an interrogation signal which excites the response circuit, and (ii) receiving a response signal generated by the response circuit. The apparatus also includes a processing unit electrically coupled to the signal transceiver. The apparatus also includes a memory device electrically coupled to the processing unit. The memory device has stored therein a plurality of instructions which, when executed by the processing unit, causes the processing unit to (a) operate the signal transceiver to (i) transmit the interrogation signal so as to excite the response circuit during fabrication of the semiconductor wafer, and (ii) measure the response signal generated by the response circuit, and (b) determine temperature of the semiconductor wafer based on the response signal of the response circuit.

Abstract: A local interconnect for an integrated circuit structure is described capable of bridging over a conductive element to electrically connect together, at the local interconnect level, non-adjacent conductive portions of the integrated circuit structure. After formation of active devices and a conductive element of an integrated circuit structure in a semiconductor substrate, a silicon oxide mask is formed over the structure, with the conductive element covered by the silicon oxide mask. Metal silicide is then formed in exposed silicon regions beneath openings in the mask. The portion of the silicon oxide mask covering the conductive element is then retained as insulation. A silicon nitride etch stop layer and a planarizable dielectric layer are then formed over the structure. An opening is then formed through such silicon nitride and dielectric layers over the conductive element and exposed metal silicide regions adjacent the conductive element.

Abstract: A power on reset cell is disclosed capable of accommodating faster power cycling rates and providing better trip point control. When the input supply voltage ramps up, the output of the power on reset cell transitions when the input is greater than a predetermined value. The power on reset cell includes a discharge circuit that is capable of discharging a subcircuit of the power on reset cell when the input supply voltage ramps down so that the output of the power on reset cell is prevented from prematurely transitioning during a subsequent ramping up of the input due to any latent charge accumulated in the prior ramping up cycle. The discharge circuit allows the power on reset cell to undergo faster power cycling without providing an invalid output. Furthermore, the discharge circuit provides better control of the output trip point.