Abstract: A cache memory control architecture within a RAID storage subsystem which simplifies the migration and porting of existing ("legacy") control methods and structures to newer high performance cache memory designs. A centralized high speed cache memory is controlled by a main memory controller circuit. One or more bus bridge circuits adapt the signals from the bus architecture used by the legacy systems to the high speed cache memory. The bus bridge circuits each adapt, for example, a PCI bus used for a particular cache access purpose to the signal standards of an intermediate shared memory bus. The main memory controller circuit adapts the signals applied to the intermediate shared memory bus to the high speed cache memory bus. The hierarchical bus architecture permits older "legacy" control methods and structures to be easily adapted to newer cache memory architectures.

Abstract: A RAID storage system which attempts to balance the I/O workload between multiple redundant array controllers is presented. The RAID storage system of the invention utilizes a plurality of redundant array controllers which require static ownership of storage devices for WRITE access requests to the same redundancy parity group. Accordingly, a plurality of storage devices are provided in the system, each of which is owned by one of the redundant array controllers. Each storage device is coupled to both its owner controller and at least one other array controller. Each array controller coupled to a storage device has the ability to read and write data from and to the storage device. Each array controller has a processing queue from which pending read and write access requests are removed and then processed one at a time by the controller. A host computer is provided for dispatching read and write access requests to the redundant array controllers.

Abstract: Decimation and interpolation of pulse code modulated (PCM) digital audio samples is performed by periodically skipping or repeating a single PCM value. A random access memory (RAM) acting as a FIFO buffer memory outputs PCM samples in response to an address output from a counter. A predetermined number of PCM samples are output from the FIFO buffer by incrementing the counter at a constant rate. Decimation is performed by doubling the incrementing rate for one read interval, and interpolation is performed by halting the incrementing for one read interval. Modifying the incrementing rate of the counter provides an economical implementation of decimation and interpolation without introducing distortion.

Abstract: A transistor gate array includes an active transistor region (50a-50n) of transistor gates all oriented in a single direction. Surrounding the active transistor region on all four sides are input/output regions (52a-52d) each containing a row of input/output transistors. All of the I/O devices on all sides of the array are oriented in the same common direction, which is the same direction as the orientation of the active transistor in the active region. This arrangement allows the use of the benefits of high angle ion implantation with fewer ion implant steps. Where some of the transistors are oriented at right angles to others, as in the prior art, four separate directions of high angle ion implantation are required to avoid degradation of electrical properties. With all transistors, including those of the gate array and those of the input/output devices, all oriented in the same direction, only two directions high angle ion implantation are required.

Abstract: Special probe pads are formed within the core of an integrated circuit, such as an ASIC, to provide direct access to internal circuitry for conducting failure analysis. For example, internal probe pads can be provided around an embedded RAM core for bit mapping the RAM core if necessary. An improved probe card is described to provide for accessing these internal probe pads using automated probing machines. The internal probe pads, preferably smaller in size than wire bonding pads, are located in available interstices on the die, preferably without increasing silicon area. Multiplexers can be used to isolate these probe pads during normal operation of the integrated circuit.

Abstract: An entity relationship diagram for a relational database is generated from introspection of the relational database to determine which entities should be included within a specific table to be displayed. Tables within the entity relationship diagram are displayed with icons hyperlinked to other portions or displays of the entity relationship diagram. A trigger icon links the displayed table to a display of the trigger information for the displayed table. A primary key icon indicates which column of the displayed table is utilized as the primary key for the displayed table, while a foreign key icon links the displayed table to a display of another table in the entity relationship diagram containing the foreign key. Dashed or dotted lines and dot or diamond terminators associated with the foreign key icon described the relationship between the displayed table and the linked table. A constraint icon links the displayed table to a display of the constraint information for an entity.

Abstract: A way of designing CPU's and computational units in an integrated circuit so that the computational unit can be designed and connected to the CPU in a modular manner. The computational unit designed for one application can be redesigned for another application without requiring a change in the CPU. The CPU has an instruction register, a first decoder connected to the instruction register to decode instruction words within a predefined set of instructions, an ALU, and buses which move operand data into the ALU and results data from the ALU. The ALU operates and the buses function responsive to the first decoder. The computational unit has an execution unit connected in parallel with the ALU to the buses, and a second decoder connected to the instruction register. The second decoder decodes only a predetermined portion of an instruction word in the instruction register when the instruction word is not in the predefined set of instructions. The execution unit operates responsive to the second decoder.

Abstract: A system and method are provided herein for creating and validating an electronic design structural description of a circuit or device from a VHDL description of the circuit or device which includes a compiler for compiling the VHDL description of the circuit or device; a device for locating problems within the compiled description and measuring the effectiveness of solving the problems; a device for passing information including the compiled description to a physical design level; a physical design tool for receiving the information and creating a physical design therefrom; and a device for back annotating the information from the physical design tool to the compiler.

Abstract: The present invention includes a method of providing data to a memory device to be read at a first frequency comprising the steps of writing data to a memory device at a second frequency; blocking the writing of data after a predetermined amount of data is written; and writing data to the memory device in response to an address. Also included is a monitor circuit comprising a monitor state machine coupled to receive inputs including a comparison result, count signals and a load enable, and configured to output a data enable signal in response to the inputs.

Abstract: An etch process selective to cobalt silicide is described for the selective removal of titanium and/or titanium nitride, unreacted cobalt, and cobalt reaction products other than cobalt silicide, remaining after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate in preference to the removal of cobalt silicide. The first step comprises contacting the substrate with an aqueous mixture of ammonium hydroxide (NH.sub.4 OH) and hydrogen peroxide (H.sub.2 O.sub.2) to selectively remove any titanium and/or titanium nitride in preference to the removal of cobalt silicide. The second step comprises contacting the substrate with an aqueous mixture of phosphoric acid (H.sub.3 PO.sub.4), acetic acid (CH.sub.3 COOH), and nitric acid (HNO.sub.3) to selectively remove cobalt and cobalt reaction products (other than cobalt silicide) in preference to the removal of cobalt silicide.

Abstract: Methods and associated apparatus for coordinating file lock requests from a cluster of attached host computer systems within I/O controllers (e.g., intelligent I/O adapters) attached to a storage subsystem. The I/O controllers, operable in accordance with the methods of the present invention, includes semaphore tables used to provide temporary exclusive access to an identified portion of an identified file. The host systems request the temporary exclusive access of a file through the I/O controllers rather than over slower network communication media and protocols as is known in the art. The I/O controllers then manages a plurality of competing lock requests to provide mutual exclusivity of the file access. The file lock management is therefore managed over the higher bandwidth storage interface channels of the host systems and without the generalized network protocols burdening the lock management process and the host system CPUs.

Abstract: Methods and apparatus for planarizing the surface of a semiconductor wafer by applying non-uniform pressure distributions to a polishing pad are disclosed. According to one aspect of the present invention, a chemical mechanical polishing apparatus for polishing a surface of a semiconductor wafer includes a polishing pad with a first surface and a second surface. The first surface of the polishing pad is arranged to contact the surface of the semiconductor wafer in order to polish the surface of the semiconductor wafer. The apparatus also includes a mechanism which is used to apply a non-uniform pressure distribution over the second surface of the polishing pad, wherein applying the non-uniform pressure distribution to the polishing pad facilitates evenly polishing the surface of the semiconductor wafer. In one embodiment, the mechanism for applying the non-uniform pressure distribution to the polishing pad is an air bladder arrangement.

Abstract: A surface mounted integrated circuit die package includes a group of peripheral leads extending laterally outwardly from the perimeter of the package and also includes an array of solder balls on the bottom of the package. The arrangement provides for a greater number of input/output connections to a die package by utilizing both peripheral leads and a ball grid array without requiring increases in package size or a reduction in the width of electrically conductive interconnections.

Abstract: Oscillating circuitry built in integrated circuitry (1) comprises a ring oscillator (31) for generating a first clock, an external oscillator (40) capable of generating a second clock in either one of two oscillating modes which is determined according to an external circuit (12 and 13, or 6 through 8) connected to terminals (2 and 3) thereof, and an internal clock selection circuit (41) which delivers the first clock as an internal clock to the integrated circuitry (1) just after the integrated circuitry (1) is activated or reset, stops the delivery of the first clock and simultaneously furnishes a signal held at a logic high level as the internal clock in response to a control signal for instructing a selection of the second clock, and then determines whether or not the external oscillator (40) is generating the second clock properly, and which furnishes the second clock as the internal clock when it determines that the external oscillator (40) is generating the second clock properly.

Abstract: Substrates having a wide range of thickness, and intended to be overmolded with a plastic package body, are accommodated in a common mold. The top surface of the substrate is provided with a dam structure, which may be formed as an additional layer on the substrate, and which is preferably in the form of a square ring. A groove (channel) is machined (e.g., by routing) into the surface of the dam structure. The top mold half, having a cavity for forming the package body, is provided with a sealing structure at the periphery of the cavity. The sealing structure has a ridge fitting into the channel of the dam structure. The depth of the groove in the dam structure is readily adjusted to ensure uniform clamping pressure of the top mold half on the substrate, so that liquid molding compound is contained within the cavity and so that undue pressure is not exerted on the substrate.

Abstract: A method for maximizing effectiveness of parallel processing, using multiple processors, to connect pins of a net of an integrated circuit is disclosed. The method requires the pins to be partitioned into sets of pins and the sets of pins to be further partitioned into meta-sets of the sets of pins. The sets and the meta-sets are connected using a minimal spanning tree algorithm, and the connected sets are made to share a pin, thereby ensuring that the whole net is interconnected without creating a loop in the routing. In addition, because the partitions and the sets of partitions average approximately the same number of pins, the work load can easily be balanced between the processors.

Abstract: A video decoder which uses a dynamic memory allocation scheme having a synchronization counter for decoder-display synchronization. The synchronization counter advantageously allows for graceful recovery from error conditions in which the decoding portion of the video decoder falls behind the display portion of the video decoder. In one embodiment, the video decoder includes an MPEG bitstream decoder, FIFO buffer logic, a free segment register, and a display processor. The video decoder decodes an encoded bitstream to obtain image data for storage in an external memory, and the display processor retrieves the image data for display on a monitor. To conserve memory, the bitstream decoder stores only anchor frames as complete images in the external memory, and bi-directional images are stored in dynamically allocated memory segments.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to a block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator which includes circuitry to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Abstract: Provided is a method and composition for obtaining consistent alignment mark profiles with both detectibiliy and detection accuracy for use in conjunction with CMP planarization processes in semiconductor fabrication. The method involves physical vapor deposition of metal over an angled, metal-lined alignment mark trench in the surface of a semiconductor wafer following wafer planarization by CMP. The shape of the trench creates a shadowing effect which produces minimal deposition in the angled region of the trench and overcomes asymmetric metal loss due to attack from slurry accumulating in the trench during CMP. The result is the formation of a reliable and reproducible alignment mark.

Abstract: A semiconductor memory device includes memory elements, each maintaining memory contents within a period of time during which a refresh operation is repeated, and a refresh request circuit for making a refresh request. The semiconductor memory device includes refreshing circuits each of which, in response to a refresh request from the refresh request circuit, performs a refresh operation on a different number of memory elements at the same time, and a selecting circuit for selecting one refreshing circuit from among the refreshing circuits according to the number of memory elements included in the semiconductor memory device. The refresh request circuit can change the interval at which it makes a refresh request.