Abstract: A phase-locked loop circuit including a divider unit that receives a serial data stream at its input and generates a parallel data stream. The parallel data stream has a slower clock rate than the serial data stream according to the present invention. A phase detector unit has an input connected to the output of the divider unit for receiving the parallel data stream generated by the divider unit. The phase-locked loop circuit further includes a voltage controlled oscillator having an input connected to the output of the phase detector unit. The output of the voltage controlled oscillator is connected to another input of the phase detector, wherein the phase detector unit generates error signals that are sent to the voltage controlled oscillator.

Abstract: An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special "checkerboard" arrangement also provided. Connections between the bumps and the edge of the die surface are shown.

Abstract: A process for optimizing the layout of an integrated circuit (IC) design is described. The optimization process includes selecting a segment of a conductive line to be modified. The segment is selected based upon its location between a first line and a second line and is separated from these lines by unequal distances, such that the segment is close enough to the first line such that a sensitive area that is susceptible to damage from particle contamination exists. The process also includes repositioning the selected segment such that the distance between the segment and the first line is increased and the distance between the segment and the second line is decreased.

Abstract: A method is presented for depositing a low stress, highly conformal metal thin film, such as tungsten, on a substrate. A substrate is provided, and is heated to a first temperature. A first portion of the metal thin film is deposited on the substrate by reacting a first set of process gases. The deposition of the first portion of the metal thin film is stopped after a first length of time, and the substrate is heated to a second temperature, which is greater than the first temperature. A second portion of the metal thin film is deposited on the substrate by reacting a second set of process gases. The second portion of the metal thin film comprises the same metal as the first portion of the metal thin film. The deposition of the second portion of the metal thin film is stopped after a second length of time. Semiconductor devices having a low stress, highly conformal thin film are also described.

Abstract: A process is described for forming self-aligned contacts to an MOS device on an integrated circuit structure characterized by the simultaneous formation of the metal silicide gate portion and the metal silicide source/drain portions. The process comprises forming a gate oxide layer on a silicon substrate, forming a polysilicon gate electrode layer over the gate oxide layer, and forming a layer of a first insulation material over the polysilicon gate electrode layer. Metal silicide is simultaneously formed on the exposed surface of the polysilicon gate electrode and over the exposed portions of the silicon substrate. Source/drain regions are formed in the silicon substrate, either before or after formation of the metal silicide over the exposed portions of the silicon substrate, whereby the metal silicide portions on the substrate above the source/drain regions are in electrical communication with the source/drain regions.

Abstract: A slurry for chemical-mechanical polishing comprises a high pH solution with particles of a catalyst mixed with the high pH solution for accelerating the polishing rate. The catalyst preferably is a metal selected from the group consisting of platinum, silver, palladium, copper, rhodium, nickel, and iron. The catalyst may be impregnated into a polishing pad used to apply the slurry to a surface. A CMP process for metal surfaces includes applying a slurry to a metal surface to be polished, and providing an electrical bias to the workpiece and to the slurry for controlling the polishing rate. The electrical bias is provided to dies in the workpiece by means of an electrical connection between a bias voltage source and scribe lines between adjacent dies.

Abstract: A stiffener device for use with a flip chip packaging assembly including a generally rectangular, plate-like member having a substantially uniform thickness. At each of the rectangular plate-like member is a curved chamfer portion extending from an upper surface to a lower surface thereof, and defined by a chamfer edge commencing at one side edge forming the respective corner and terminating at an opposite side edge of the respective corner. Each curved chamfer portion is adapted to receptively accommodate a respective mounting bolt therethrough. The fabrication of the stiffener device is formed from a single stamping or punching operation in a manner maintaining a substantially planar upper surface and lower surface.

Abstract: A method for dynamic reconfiguration of a message-passing interface from a Push model to a Pull model is disclosed. In the Push model, a host computer device moves data stored in a host local memory to an I/O peripheral shared memory, whereas in the Pull model, the I/O peripheral moves data from the host's shared memory to a local memory of the I/O peripheral. To dynamically reconfigure the message passing interface from the Push to the Pull model, the hosts waits for the I/O peripheral to cycle through power-on/reset, locates the I/O peripheral's inbound and outbound queues in memory, directs the I/O peripheral to clear its outbound queue of messages from previous inbound messages and initializes the allocated message frames as free messages. The host then posts a message to the I/O peripheral inbound queue instructing the I/O peripheral to initialize in the Pull model. The I/O peripheral then posts any messages currently being processed to the I/O peripheral outbound queue.

Abstract: The present invention presents a mobile station of a wireless communications system such that when the mobile station is in idle mode (i.e., listening to a paging channel periodically, but otherwise taking no action), the control processor commands the mobile station to enter into sleep mode to minimize power consumption. During sleep mode, the high-frequency reference clock and thus all high-frequency clocks derived from it are turned off. Only a low-frequency clock remains operating at all times to clock the sleep logic.

Abstract: A redundant storage control module (also referred to as RDAC or multi-active controller) maintains a queue of pending I/O requests sent for processing via a first asynchronously operating I/O path. In the event of failure of the first asynchronously operating I/O path, the controller restarts the entire queue of pending I/O requests to a second I/O path without waiting for each request to individually fail from the first path. Some prior techniques required the RDAC module to await failure of each I/O request sent to the failed first I/O path before restarting each failed request on the secondary I/O path. Such techniques greatly extend the total time required to restart all operations sent to a failed I/O path, by awaiting the failure of all I/O requests previously sent to the first I/O path.

Abstract: An object-oriented, multi-media architecture provides for real-time processing of an incoming stream of pseudo-language byte codes compiled from an object-oriented source program. The architecture includes a plurality of processors arranged for parallel processing. At least some of the processors are especially adapted or optimized for execution of multi-media methods such as video decompression, inverse discrete cosine transformation, motion estimation and the like. The architecture further includes a virtual machine computer program that reconstructs objects and threads from the byte code stream, and routes each of them to the appropriate hardware resource for parallel processing. This architecture extends the object-oriented paradigm through the operating system and execution hardware of a client machine to provide the advantages of dedicated/parallel processors while preserving portability of the pseudo-language environment.

Abstract: A conveying assembly in a conditioning sub-assembly for conveying a conditioning surface to a polishing pad during conditioning is described. The conveying assembly includes an arm and a guiding component connected to the arm and adapted to guide the conditioning surface about the conveying assembly, thereby allowing another area of the conditioning surface to advance and become available for conditioning.

Abstract: A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator modified to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Abstract: A data processing system that includes an improved architecture for providing hot spare storage devices. Specifically, the data processing includes a bus that is connected to one or more computer systems and a number of storage subsystems. Each storage subsystem includes storage devices and a controller. The controller in a storage subsystem provides the connection to the bus and an interface for controlling data transfers to and from the storage device. A backup storage system is connected to the bus. The data processing system also includes a detection means for detecting a failure of a storage device within one of the plurality of storage subsystems and a backup means for using the backup storage device to replace the failed storage device.

Abstract: Generally, a method checks the error signals of the interleaves to determine if the number of error bursts, burst error lengths or burst size is exceeded. These values are predetermined limits. To this end, the present invention tracks the number of errors and attempts to "fit" the errors in the programmed parameters of the burst size and burst limit values, such as illustrated above. If there is no fit, then an error signal is provided by burst limit checker.

Abstract: A method and apparatus for controlling access to a bus. A target having a period of unavailability is identified. A master device requesting access to the bus to initiate a data transfer between the master device and the target device also is identified. The master device is denied access to the bus for a delay period in response to the master device attempting to retry a data transfer with the target device, wherein the delay period is a time period after which the target device becomes available for additional transfers, wherein the bus is available to other master devices during the delay period.

Abstract: An end effector to facilitate conditioning of a surface of a polishing pad used in chemical-mechanical polishing of an substrate surface is described. The end effector includes a rigid body including a contact surface capable of being attached to a conditioning disk and having a predetermined non-planar region that is adapted to at least one of (i) effectively maintain a non-planar area on the surface of the polishing pad and (ii) shape the polishing pad, when the end effector is employed to condition the polishing pad.

Abstract: A novel semiconductor fabrication chamber includes a quartz vessel and a metal vessel with a resilient sealing member disposed between the quartz and metal vessels to define a vacuum chamber, along with a cooling assembly mounted on a quartz flange extending around the perimeter of the quartz vessel. A liquid or gaseous cooling medium is passed through the cooling assembly to reduce the operating temperature of a portion of the resilient sealing member in contact with the quartz flange during semiconductor fabrication processing so as to extend the useful life of the sealing member. The cooling assembly is secured to the quartz flange using a plurality of clamping fixtures for easy installation and retrofitting.

Abstract: An electronic semiconductor device package, the package comprising: a substrate having traces; a die attached to the substrate; first level interconnects of the die to the traces of the substrate; and a stiffener attached to the substrate, wherein the stiffener comprises at least one clip. A system for attaching a heat sink to an electronic semiconductor device package, the system comprising: a stiffener of the electronic package which is attachable to the electronic package; and at least one clip that is integral with the stiffener and secures the heat sink to the stiffener. A method of detachably attaching a heat sink to an electronic semiconductor device package, the method comprising: attaching a stiffener to the package, wherein the stiffener comprises at least one clip; positioning a heat sink adjacent the stiffener; and engaging the clip with the heat sink, wherein the heat sink is secured to the stiffener by the clip.

Abstract: An recovery circuit is described for recovering data from serially transmitted digital signals wherein a very long hold time and infinite phase range is desired. The recovery circuit includes a variable delay line, a data tracking phase-locked loop (PLL), a clock tracking phase-locked loop, a phase sensor, and a switch. The variable delay line is responsive to a feedback signal and a clock signal for generating a first delayed phase-locked signal. The data tracking phase-locked loop is responsive to the first delayed phase-locked signal and a data signal for producing a data phase error signal. Similarly, the clock tracking phase-locked loop is responsive to the clock signal for providing a second delayed phase-locked signal. Responsive to both of the delayed phase-locked signals is the phase sensor which provides a select output signal when the phase-locked signals are in phase with each other.