Abstract: According to the present invention, a single chip semiconductor devices is provided. In one version of the invention, a single chip CMOS technology architecture is used to implement all or various combinations of baseband radio transmission, baseband interfaces and filtering, source coding, source interfaces and filtering, control and supervision, power and clock management, keyboard and display drivers, memory management and code compaction, digital signal processing ("DSP") and DSP memory and radio interface functions.

Abstract: In a multiprocessor data processing system including at least one main processor and one sub-processor utilizing a shared queue, queue integrity is maintained by associating a semaphore with each queue entry to indicate ownership of that queue entry. Ownership of a queue entry is checked by a processor attempting to post to the queue entry. Upon determining that the queue entry is available to the processor, the queue entry is loaded by an atomic write operation, ownership of the queue entry transferred to another processor, and the other processor may be alerted of the post to the queue. The other processor maintains ownership of the queue entry until the other processor has read and saved the data from the queue entry. Items may thus be posted to the queue and cleared from the queue by a processor independent of the state of the other processor.

Abstract: The testing of integrated circuits in a plurality of dice arranged in rows and columns in a semiconductor wafer is facilitated by effectively increasing the pitch between adjacent input/output bonding pads on each die by providing a plurality of test pads in scribing space between adjacent die. Alternate test pads are connected with alternate bonding pads on adjacent die, thereby effectively increasing the pitch of adjacent die for testing. After the integrated circuits are tested and defective circuits are marked, the wafer is scribed in the scribe space and broken to recover the individual die or integrated circuit chips.

Abstract: A pattern data generating system solves a problem of a conventional pattern data generating system in which the total processing time is prolonged. The present pattern data generating system includes a parallel processing number calculator for computing the number of parallel processes to be used by a region divider that sequentially distributes the split pattern data. A group of pattern data generators generate pattern data in parallel processes. A pattern data combiner combines the pattern data output from the pattern data generators. A parallel processing controller controls the processing.

Abstract: A Tape-Automated-Bonding (TAB) package includes a resilient polyimide layer that supports a metal leadframe. A microelectronic circuit die is mounted in a hole in the polyimide layer and interconnected with inner leads of the leadframe. The TAB package is adhered to a support member having spacers that abut against the surface of a printed circuit board (PCB) on which the package is to be mounted and provide a predetermined spacing between the leadframe and the surface. Outer leads that protrude from the leadframe are bent into a shape so as extend, in their free state, toward the surface at least as far as the spacers. The package and support member assembly is placed on the PCB surface, and the combination of the weight of the assembly, the resilience of the leads and the preset standoff height enable the leads to resiliently deform so that the spacers abut against the surface and the leads conformably engage with the surface for soldering or other ohmic connection to conjugate bonding pads on the surface.

Abstract: A linear interpolator for determining a weighted average between first and second terms having first and second weights, respectively. The linear interpolator includes a first multiplier for multiplying the first term and an inverse of the second weight to produce a first set of partial products, a second multiplier for multiplying the second term and the second weight to produce a second set of partial products, a carry-save addition ("CSA") tree and an adder. The CSA tree and adder combine the first set of partial products, the second set of partial products, and the first term to produce the weighted average. In another embodiment, the linear interpolator includes a plurality of multiplexers (muxes), the number of muxes being equal to the bit width of the second weight. Each mux selects between the first and second term, depending on whether the corresponding bit of the weight is a zero or one, to produce a plurality of partial products.

Abstract: An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage in the Vector FIFO buffer when it is desired to soft-mute an audio output of the decoder.

Abstract: An asynchronous transfer mode (ATM) digital electronic communication system includes an ATM communication system interconnection and termination unit (ATMCSI/TU). This ATMCSI/TU includes both a programmable microprocessor and several hardware-implemented coprocessors. The hardware-implemented coprocessors are under control of the microprocessor, and are dedicated to the performing of repetitive tasks. Thus, the microprocessor is freed to perform supervisory tasks in the ATM in addition to performing tasks associated with actual communication of digital data packages (i.e., CS-PDU's) in the ATM system. Thus, the APU is freed from doing repetitive data manipulation tasks, while these tasks are performed by one or more hardware-implemented coprocessors using memory mapped data structures and linked lists of data.

Abstract: A differential current mode driver is provided with output source and sink currents that remain nearly equal in magnitude and opposite in direction throughout normal, power-down, and power-up modes of operation. Three time constants are employed to regulate these different modes of operation. The differential current mode driver includes a first time constant to stabilize the output source and sink currents during the on-state, a second time constant to control the transition from the on-state to tristate, and a third time constant to control the transition from tristate to the on-state, all the while maintaining equal source and sink currents.

Abstract: A fully digital clock multiplier capable of generating any N/M multiple of an input clock frequency with a precise duty cycle is provided. The input clock signal is divided by M to create a divided clock signal. The propagation of the input clock signal along a delay cell string during a half cycle of the divided clock signal is then measured. The measured propagation is then scaled by a factor N to select an appropriate delay cell string length within a ring oscillator for generating an output signal.

Abstract: This interconnect chip provides the function of an antifuse device. The interconnect chip is initially disconnected. Application of a high voltage applied across two terminals on the chip causes intrinsic polysilicon, which serves as an insulator between the connections to break down and form a reliable short circuit between the pads by redistribution of impurities from the layers above and below the intrinsic polysilicon.

Abstract: A gate array is disclosed having a programmable polysilicon layer which serves as both the gate electrodes for MOS transistors and routing lines for some connections between gate electrodes. The gate array structure is formed on a semiconductor substrate and has an array of identical base cells located in a core region of the structure. Each such base cell des the following elements: (1) a plurality of transistors, each of which includes a gate electrode; and (2) one or more gate connection strips formed on the substrate and electrically connecting selected gate electrodes of two or more of the transistors. Preferably, the gate connection strips are made from the same material as the selected gate electrodes (e.g., polysilicon) and are integrally connected therewith. The gate connection strips may patterned (i.e., programmed) to form substrate level routing between gates of various transistors.

Abstract: A method for transferring data from a first device to a second device where the second device has a main data processor and a secondary processor associated therewith. The method includes the steps of (1) transferring a data stream having a control portion and a data portion from the first device to the second device, and (2) processing the data portion with the secondary processor in accordance with the control portion without interrupting the main data processor. A multi-controller apparatus which is useful for practicing the method is also disclosed.

Abstract: To provide high purity gases to manufacturing tools, a gas isolation box is employed which is formed of stainless steel and includes vertical slots for receiving gas stick carrier cards. Gas sticks include required valves, gauges, and regulators rigidly mounted on stainless steel carrier cards, leak tested and labeled. The carrier cards with the rigidly mounted, leak tested gas sticks are slid into the vertical slots of the gas isolation box. Only two connections are then required to complete to gas lines, reducing the potential for flexing of high purity gas lines during installation.

Abstract: A method of setting a plurality of addresses is disclosed. The method includes the step of setting a first module identifier for a first device module. The method further includes the step of setting a first address for a first device, said first address comprising an upper section and a lower section. The method also includes the step of setting a second address for a second device, said second address comprising an upper section and a lower section, wherein the step of setting the first address for the first device includes the steps of setting the upper section of the first address to the first module identifier, and setting the lower section of the first address to a first value; and wherein the step of setting the second address for the second device includes the steps of setting the upper section of the second address to a second value, and setting the lower section of the second address to the first module identifier.

Abstract: An MPEG audio decoder includes a Vector FIFO buffer and a windowed polyphase filter. Groups of vector samples are zeroed out prior to storage (or after storage, if desired) in the Vector FIFO buffer when error concealment is performed.

Abstract: In one embodiment, a method of forming a barrier layer for contacting a metal interconnect layer to one or more exposed N and P type silicon regions on a wafer. The wafer is heated with a direct radiation source, such as a lamp. To equalize the differing emissivities of the N type and P type silicon regions, an opaque layer of refractory metal is first formed on the regions at a temperature below approximately 100.degree. C. A refractory metal deposition process is then conducted at temperatures between 230.degree. C.-425.degree. C. During this higher temperature deposition process, the reducing gas is ramped up with time to increase the deposition rate of the refractory metal as the exothermic reducing reactions increasingly heat the contact areas.

Abstract: An on-chip driver is described for applications voltage output signals are desired from a digital sub-micron CMOS integrated circuit. The driver includes a signal buffer, signal level shifter, output pull-up, and an output pull-down. The signal buffer is coupled to a digital CMOS input for generating a corresponding buffered signal that is received by both the output-up down and the level shifter. The output pull-down is responsive to the buffered signal and operates to pull the output of the driver to a low voltage level of about 0 volts when the digital CMOS input is at a low logic state. Further, the level shifter is responsive to the buffered signal for generating a voltage shifted signal that is received by the pull-up which pulls the output of the driver to a high voltage level of 2.5 volts or greater when the digital CMOS input is at a high logic state.

Abstract: A network adapter formed on a single semiconductor substrate. The network adapter includes a host bus interface circuit adapted to be connected to a host data bus. A buffer memory is connected to the host bus interface circuit and temporarily stores digital information received from the host data bus. The digital information received from the host data bus are reformatted into packets according to a network protocol by a reformatting circuits. A processor and a network interface circuit are connected to the reformatting circuits. The processor controls the reformatting of the digital information. The network interface circuit is adapted to be connected to a digital network employing the network protocol.

Abstract: A process of conditioning a polishing pad used in chemical mechanical polishing of an integrated circuit and having a glazed layer is described. The process includes introducing a conditioning reagent including at least one of hydrofluoric acid, buffered oxide etch composition and potassium hydroxide on the polishing pad to dissolve at least a portion of the glazed layer; and abrading the glazed layer and disloding at least some particles from the glazed layer.