Abstract: A computer implemented method for optimizing cell placement for integrated circuit design is provided herein. The method comprises the steps of segmenting an integrated circuit surface abstraction into a plurality of regions; assigning a plurality of cells to one of the regions; creating a list of said plurality of cells in order of decreasing cell height; reassigning said cells in order of the list such that the cells are assigned to said region until there is insufficient capacity to fit anymore of the cells into the region; and thereafter assigning the remaining cells outside of the region.

Abstract: A cell placement for an integrated circuit chip comprises a large number of cells allocated to respective locations on the surface of the chip. The placement is divided into switch boxes that surround the cell locations respectively. A bounding box is constructed around each net of a netlist for the placement. A congestion factor is computed for each switch box as being equal to the number of bounding boxes that overlap the respective switch box. A cost factor for the placement and associated netlist is computed as the maximum value, average value, sum of squares or other function of the congestion factors. The individual congestion factor computation can be modified to require that a pin of a net of one of the bounding boxes overlap or be within a predetermined distance of a switch box in order for the congestion factor to be computed as the sum of the overlapping bounding boxes in order to localize and increase the accuracy of the cost factor estimation.

Abstract: A frame memory interface architecture which is easily adaptable to interface to any of a plurality of frame memory storage architectures. In the preferred embodiment, the present invention comprises an MPEG decoder system and method for decoding frames of a video sequence. The MPEG decoder includes various slave devices which access a single external memory, wherein these slave devices include reconstruction logic or motion compensation logic, a reference frame buffer, display logic, a prefetch buffer, and host bitstream logic, among others. Each of the slave devices is capable of storing or retrieving data to/from the memory according to different frame storage formats, such as a scan line format, a tiled format, and a skewed tile format, among others. The frame memory interface is easily re-configurable to each of these different formats, thus providing improved efficiency according to the present invention. The slave device then generates a request to the memory controller.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a-high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A semiconductor device package containing a semiconductor die uses a platform mounted on an active face of the die. The platform electrically connects to at least one bond pad on the die. A package lid electrically connects to the platform on the die and a package case connection. The package case connection is also electrically connected to at least one external connector on the package. The platform and package lid thereby connect the at least one bond pad on the die to the at least one external connector on the package. Using the platform and lid for electrical connections from the semiconductor die bond pads to the external package connector reduce the number of bond fingers required to surround the perimeter of the die. The package lid and platform may, for example, be used for ground or power connections to the die bond pads.

Abstract: The present invention includes an apparatus for supporting a device in a computer comprising a base, preferably juxtaposed to a connector, and a ledge extending from the base section. The base preferably defines a channel to fit the apparatus to the connector. The channel can be defined by arms that are included in the base. At least one support strut extends between the base and the ledge. A disk drive is supported by the apparatus. The disk drive is seated against the ledge to provide support and to attenuate vibrations caused by the rotating disk. Preferably, the apparatus is seated against a motherboard so that the connector does not bear the weight of the disk drive. One modification of the present invention integrates the connector and the apparatus.

Abstract: According to one aspect of the invention, a semiconductor package is provided including a package substrate having an upper surface and a lower surface, wherein electrical contacts on the lower surface of the substrate are coupled to corresponding electrical contacts on a printed circuit board by a plurality of solder balls; a semiconductor die having a non-active surface and an active surface, wherein the active surface is electrically coupled to the upper surface of the package substrate by a plurality of solder bumps; and an integrated heat spreader and ring stiffener coupled with the non-active surface of the semiconductor die by a phase change material which is retained by a miniature dam ring while in a liquid state, wherein heat generated by the die is transferred to the heat spreader, and wherein the heat spreader has a protrusion formed thereon which matches the outermost size of the die.

Abstract: Provided is a single-piece integrated heat spreader/stiffener which is bonded to the substrate and die in a semiconductor package following electrical bonding of the die to the substrate, a packaging method using the integrated heat spreader/stiffener, and a semiconductor package incorporating the integrated heat spreader/stiffener. In a preferred embodiment, the integrated heat spreader/stiffener is a piece of high modulus, high thermal conductivity material shaped to attach over a die on the surface of a packaging substrate. The heat spreader/stiffener is equipped with a plurality of apertures to provide access to the top surface of the die for adhesive to bond the heat spreader/stiffener to the die, and to its perimeter to provide access for dispensation of underfill material between the die and the substrate. Once the adhesive and underfill materials are in place, the adhesive and underfill resins are cured by heating.

Abstract: A process for implementation on a programmed digital computer includes providing a placement of clusters of cells which are assigned to regions on an integrated circuit chip, and combining the regions to form region groups. The region groups collectively constitute a "jiggle" which resembles a sieve. The clusters in each region group are re-assigned to the regions in the region group. The regions are recombined to form different region groups (a different jiggle), and the clusters in each different region group are re-assigned to the regions in the different region group. These steps are repeated using at least two, preferably four different jiggles, until an end criterion is reached. Then, the regions and clusters are hierarchically subdivided, and the process is repeated for each hierarchical level until the clusters have been reduced to individual cells.

Abstract: A method for testing a memory device which statistically characterizes the failure time for a subset of cells sampled from the memory array before performing testing of the memory array in general. The memory device includes a testing unit which determines the failure times for cells in the sample subset, and a parameter calculation unit which computes one or more statistical parameters from the failure times. These statistical parameters are then used to determine a refresh pause time which is used in a data retention test of the memory array. The testing method may be performed when power is applied to the memory device. Thus, the BIST method may provide for the accurate detection of memory faults in the memory array at any power-up temperature. In addition, the testing method may be performed after the memory array attains an operational temperature, or in response to an operating system command.

Abstract: A machine-independent operating environment, method and storage medium embodying machine-code usable by a computer system for exchanging design information between a plurality of computer-aided design tools. A set of data format objects are provided for exchanging the design information between each computer aided-design tool. An accessing method is provided for enabling each computer-aided design tool to store the design information into and retrieve the design information from an associated data format object. An archiving method is provided for enabling the computer system to write the data format objects storing the design information onto and read the data format objects storing the design information from a storage device interconnected with the computer system using each associated data format object. Preferably, each computer-aided design tool is expressed in machine-portable object code which is executed by a virtual machine on the computer system.

Abstract: One aspect of the invention relates to a method for providing a semiconductor package with a thermally conductive coating, the semiconductor package including a package substrate having a plurality of electrically conductive traces formed thereon, an upper surface and a lower surface, the lower surface having a plurality of contacts for providing electrical connection between the conductive traces formed on the package substrate and a plurality of conductive traces formed on a printed circuit board, and a semiconductor die mounted to the upper surface to the package substrate, the semiconductor die having a plurality of bond pads formed thereon which are electrically connected to the conductive traces formed on the package substrate. In one embodiment, the method includes the steps of depositing a coating on the upper surface of the package substrate and the coating includes a diamond film or diamond particles.

Abstract: A DRAM array embedded in an IC, ASIC or a SLIC includes a plurality of redundant functional elements and a substitution circuit which responds to signals communicated from a bus to electrically connect selected ones of the redundant elements as fully functional replacements for corresponding defective elements of the DRAM array. The redundant elements include bit blocks and word line groups. The substitution circuit includes a controllable selector which electrically connects selected ones of the bit blocks and word lines to respond to data and address signals communicated on the bus. A register responds to bus control signals and supplies signals to achieve connection of the redundant elements. The defective elements are identified, and the replacement redundant elements are substituted, by testing the elements of the DRAM array for proper functionality and processing the results of the test.

Abstract: A serial data interface device is coupled to electronic devices or other data transmitters or receivers, such as disk, optical, tape or CD-ROM drives, computers, printers, etc. The interface includes first and second ports capable of receiving and transmitting information to respective electronic devices, and first and second storage devices, such as frame buffers, for storing information. Each of the storage devices is coupled to both the first and second ports and are coupled to another electronic device. Included in each storage device is a main memory that is coupled to at least one of the electronic devices and at least one of the ports. A control memory that is coupled to the main memory is also included, along with a main memory arbiter that is coupled to the control memory and the main memory. Further included is a buffer allocation control that is coupled to the at least one electronic device and at least one of the ports.

Abstract: A process is disclosed for forming one or more doped regions beneath the surface of a single crystal semiconductor substrate, such as retrograde wells or deeper source/drain regions, by implantation at low energy which comprises orienting the crystal lattice of the semiconductor substrate, with respect to the axis of the implantation beam, i.e., the path of the energized atoms in the implantation beam, to maximize the number of implanted atoms which pass between the atoms in the crystal lattice. This results in the peak concentration of implanted atoms in the crystal lattice of the single crystal semiconductor substrate being deeper than the peak concentration of implanted atoms in the substrate would be if the axis of the implantation beam were not so oriented with respect to the crystal lattice of the semiconductor substrate during implantation.

Abstract: On integrated circuit designs employing large, pre-defined circuit blocks, chip area utilization and signal routing is improved by permitting signals between circuit blocks surrounding (e.g., on opposite sides of) a large circuit block (megacell) to physically pass through the megacell. The megacell is laid out so that a "parting line" is defined through the megacell. Circuits within the megacell are laid out so that no circuit "straddles" the parting line. The megacell can then be split or stretched about the parting line to create a wiring channel. The wiring channel is used for routing signals from the surrounding cells (circuit blocks) through the large circuit block (megacell). Signals between the separated portions of the stretched or split megacell on opposite sides of the parting line may be routed in one metal layer, while connections of surrounding cells through the megacell may be routed in another metal layer.

Abstract: A Motion Picture Experts Group (MPEG) video/audio data bitstream comprises frames of encoded audio data, each of which includes a plurality of integrally encoded subframes, which are decoded by an audio decoder for presentation. A synchronization unit controls the decoder to skip a subframe if a predetermined decoding time for the subframe is earlier than a current time, and to repeat the subframe if the predetermined decoding time is later than the current time. A typical MPEG audio frame includes 12 subframes, such that skipping or repeating a subframe is 1/12 as noticeable as skipping or repeating an entire frame. A buffer memory stores one or more subframes prior to decoding, such that the subframes can be skipped or repeated by manipulation of a read pointer for the memory.

Abstract: Disclosed is a failure analysis tool including a production tester electrically coupled to a test IC in such a manner that it can test the IC in a conventional manner (e.g. by providing a series of dynamic vectors), and also provide an OBIC signal to an OBIC detection system. This is accomplished by providing power to the IC through a voltage source having a non-zero internal resistance while the OBIC signal is generated, thus preventing the OBIC signal from shorting to ground when it is received at the power supply. Failure analysis is conducted by first performing functional testing with a production tester until a failing state is identified. While this functional testing is being performed, the internal resistance of the voltage source is set to zero. Then, when the failing state is identified, the internal resistance of the voltage source is set to a non-zero value and the IC is scanned by an optical beam to generate OBIC signals indicating the locus of the failure.

Abstract: A microprocessor is configured to fetch a compressed instruction set which comprises a subset of a corresponding non-compressed instruction set. The compressed instruction set is a variable length instruction set including 16-bit and 32-bit instructions. The 32-bit instructions are coded using an extend opcode, which indicates that the instruction being fetched is an extended (e.g. 32 bit) instruction. The compressed instruction set further includes multiple sets of register mappings from the compressed register fields to the decompressed register fields. Certain select instructions are assigned two opcode encodings, one for each of two mappings of the corresponding register fields. The compressed register field is directly copied into a portion of the decompressed register field while the remaining portion of the decompressed register field is created using a small number of logic gates.

Abstract: In a multifunction PCI device containing identical backend functions or other large, redundant functional blocks, a single backend function is selected as a primary function while in test mode. All backend I/O channels are then simultaneously tested in parallel, with the same data and control signals from a PCI local bus being driven to all backend channels during the same test clock cycle. A single backend channel is designated as the primary for providing requisite handshaking signals during output to the backend I/O channels. Input data from each backend channel is received in parallel and compared, with miscompares being flagged to allow testing of the input data path from the respective backend I/O channel. Only signals from the primary backend I/O channel are designated for transmission to the PCI local bus. Signals from the remaining backend channels are received in parallel with and compared to the signals from the primary channel, and miscompare flags are generated for any discrepancies identified.