Abstract: An integrated circuit includes a ground plane structure which provides a uniform ground potential throughout the integrated circuit and improves its performance. The ground plane structure is carried atop the active circuit elements of the integrated circuit and connects with each of the ground-potential contact pads of the circuit. A method of making the integrated circuit includes applying a ground plane precursor structure over all of the integrated circuit topology, and removing portions of the precursor structure where the ground plane is not desired. A method of providing bump structures at each of the contact pads for use in TAB bonding of the electrical connections of the integrated circuit to a package structure is also set forth.

Abstract: A latching comparator includes first and second current integration nodes having first and second integration capacitances, respectively. A current source applies a first tail current to a current steering circuit which steers the tail current onto the first and second current integration nodes as a function of first and second data signals. An offset adjustment circuit is coupled to the first current integration node for adjusting the first integration capacitance relative to the second integration capacitance. A latch circuit is coupled to the first and second current integration nodes and has a data output.

Abstract: A semiconductor die is mounted to a die receiving area, which is defined by inner ends of conductive leads to which the die is connected. The die is temporarily retained in a substantially fixed position relative to the die receiving area by various techniques for the purpose of permitting bond wires to be attached between the conductive leads and the die. Preferred techniques include employing a mechanical chuck, dispensing an adhesive between the die and its die receiving area, and forming an ultrasonic bond between the die and the die receiving area. Once electrical connections between the die and the conductive lines are formed, the die need not be retained in a fixed position, as the electrical connections will provide sufficient support for the die. Accordingly, conventional die attach techniques, which expose the semiconductor die to substantially elevated temperatures, are avoided.

Abstract: Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclosed. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons, by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes to be accommodated. Polydirectional non-orthogonal three layer metal routing is disclosed. The architecture may be combined with the tri-directional routing for a particularly advantageous design. In the tri-directional routing arraingement, electrical conductors for interconnecting terminals of microelectronic cells of an integrated circuit preferrably extend in three directions that are angularly displaced from each other by 60.degree.. The conductors that extend in the three directions are preferrably formed in three different layers. A method of minimizing wire length in a semiconductor device is disclosed. A method of minimizing intermetal capacitance in a semiconductor device is disclosed.

Abstract: A method and apparatus provides a method for polishing a surface of a substrate with a polishing pad. The surface of the substrate is polished using the polishing pad. The surface of the substrate is deformed in response to changes in the polishing pad, wherein deformation of the surface of the substrate increases uniformity in polishing of the surface of the substrate.

Abstract: A polishing pad surface designed for chemical mechanical polishing of substrates is described. The polishing pad includes a first area of the surface having formed thereon a first set of grooves and a second area of the surface having formed thereon a second set of grooves, wherein the first set of grooves have a larger cross-sectional area than the second set of grooves.

Abstract: A single chip network adapter apparatus has each component disposed on a single semiconductor chip. The network adapter includes a host interface circuit which is adapted for connection directly to a host system bus. The host interface circuit sends information to and receives information form the host system bus, and has random access memory coupled thereto. A processor is coupled to the random access memory and formats information received from the host system bus to a network protocol format. The processor also converts information received in a network protocol format to a form suitable for the host system bus. A network interface circuit is coupled to the random access memory and is adapted for connection directly to a network. The network interface circuit sends information formatted by the processor to the network and receives information to be converted by the processor from the network.

Abstract: According to the present invention, a semiconductor package is provided. In one version of the invention, the semiconductor package includes a laminated substrate having a semiconductor die mounted on its upper surface, electrical connections between bond pads on the semiconductor die and conductive traces on the substrate, as well as electrical connections between the conductive traces and electrical contacts on the lower surface of the substrate. The semiconductor package also includes a molded covering on the upper surface of the substrate which covers the semiconductor die and the electrical connections. The molded covering has a mold body portion and a mold gate runner which extends from the mold body portion to an edge of the substrate. The mold gate runner is provided with a surface that is substantially even with the edge of the substrate and rises perpendicularly from the upper surface of the substrate.

Abstract: An integrated circuit package having a die supported on a ball grid array substrate and wire bonds electrically connecting the die to the substrate. Supported on the substrate is a lock ring having a threaded opening encircling the die. Encapsulant covers the die and the wire bonds and adheres the lock ring to the substrate. A heat sink having a threaded portion can be threaded into the lock ring into an operative cooling position relative to the die and subsequently to an unthreaded removed position. When in the latter position, a repair station can be positioned over the package and the solder balls are accessible for hot gas melting thereof for removal (or replacement) of the package from the underlying motherboard.

Abstract: An method for designing integrated circuits for a serial scan test using an improved, modular flip-flop cell is presented. The modular flip-flop cell has a delay element strategically placed in the serial scan chain to reduce the occurrence of hold time violations. The delay element is located in a test path along the serial scan chain. The delay element causes the hold time of the test input terminal to be non-positive, ensuring that there are no hold time violations, while not affecting the time delay on the normal data path.

Abstract: A method for providing a nonfunctional circuit design for evaluation in accordance with a static timing analysis is provided herein. The method initially generates a netlist, and then creates a standard delay format (SDF) file from the netlist. The standard delay format file contains occurrence names and delays associated with all elements of the design. The method subsequently selects elements of the design, alters the functionality of each selected element, and alters the standard delay format file entries corresponding to each selected element. The functional alteration of selected elements comprises altering an AND gate to be an OR gate, altering a NAND gate to be a NOR gate, altering an OR gate to be an AND gate, altering a NOR gate to be a NAND gate, altering an XOR to be an XNOR, and/or altering an XNOR to be an XOR in a predetermined manner.

Abstract: An arrangement of bump pads for use on a face of a flip-chip semiconductor die. The arrangement comprises four corner regions, each corner region comprising multiple I/O bump pads and power bump pads. The corner regions are specialized bump arrangements depending upon the size of the die, signal to power ratios, and the core power requirements. The die arrangement also comprises multiple edge regions having multiple I/O bump pads and power bump pads. The edge regions are located along the edges of the die and are interleaved between the corner regions. The dimensions of the corner regions and the edge regions depend upon the power to signal ratio of the region. Also provided is a core power region having multiple power bump pads, centrally located within the edge regions and the corner groups. Core requirements mandating an odd number of rows and columns of bumps for the core require a special "checkerboard" arrangement also provided. Connections between the bumps and the edge of the die surface are shown.

Abstract: Provided is a chemical mechanical polishing pad having grooves in its polishing surface which have a sub-surface cross-sectional span greater than the grooves' surface opening span. In this way, the edges of the groove are undercut. This provides both increased groove volume for a given pad surface area and groove depth, and variable flexibility in the polishing pad's surface. Grooves in pads of the invention also typically include a neck region at the top of the groove, where the groove side walls are substantially parallel. This provides a margin for the pad to wear during polishing without affecting the pad's surface area. The invention also provides a method and apparatus for cutting grooves in a chemical mechanical polishing pad.

Abstract: An apparatus and method wherein conductive patterns are written in amorphous silicon or polysilicon deposited on an integrated circuit and used for interconnecting circuit elements contained therein. The substantially pure amorphous silicon or polysilicon is deposited onto an integrated circuit face at low temperature. A Focused Ion Beam deposition system deposits dopant atoms into the deposited pure silicon in a desired pattern. The dopant atoms are then activated by heat from a focused laser beam which adiabatically anneals the specifically doped areas of the deposited silicon. The resulting annealed doped areas of the silicon have low resistance suitable for circuit conductors. The surrounding undoped silicon remains a high resistance and a good insulator.

Abstract: A method and apparatus for transferring data from a first device to a second device connected by a controller having a parity buffer and a memory having a first storage and a second storage is disclosed. The method includes the steps of transferring first data from the first device to the first storage; transferring second data from the first device to the second storage; transferring the first data to the second device and storing the first data in the parity buffer; and determining parity data from the second data and the first data stored in the parity buffer.

Abstract: An apparatus and method for locating a good approximation of optimal Steiner tree routing in the presence of rectilinear obstacles, including finding a Steiner tree on an escape graph. The escape graph is constructed by forming lines from given points (pins) and obstacles. Obstacles and the segments of obstacles are provided with lines parallel to that segment at a given minimum distance S.sub.min from the obstacle is constructed until it reaches either a boundary of an obstacle or a boundary of the core. For pins which do belong to a boundary of an obstacle, a ray, perpendicular to the segment of the boundary on which the pin is located is constructed from the pin and out from the obstacle until it reaches another obstacle or a boundary of the core. For pins which do not belong to an obstacle, vertical and horizontal lines are constructed. A Steiner tree may then be found on the escape graph by using any number of algorithms such as algorithm S and algorithm M.

Abstract: A differential current mode driver is provided with output source and sink currents that remain nearly equal in magnitude and opposite in direction throughout normal, power-down, and power-up modes of operation. Three time constants are employed to regulate these different modes of operation. The differential current mode driver includes a first time constant to stabilize the output source and sink currents during the on-state, a second time constant to control the transition from the on-state to tristate, and a third time constant to control the transition from tristate to the on-state, all the while maintaining equal source and sink currents.

Abstract: A power system and method utilizes two independent AC lines to power an N+1 power supply configuration. The AC lines are selectively switched to supply power to the N+1 power supply configuration in response to power failure on one of the AC lines. The distribution system takes advantage of the N+1 configuration by always powering at least N power supplies. Sequencing of the switching is also monitored for incorrect power switching. Upon detection of incorrect power switching relays are forced open.

Abstract: A methodology for generating structural descriptions of complex digital devices from high-level descriptions and specifications is disclosed. The methodology uses a systematic technique to map and enforce consistency of the semantics imbedded in the intent of the original, high-level descriptions. The design activity is essentially a series of transformations operating upon various levels of design representations. At each level, the intended meaning (semantics) and formal software manipulations are captured to derive a more detailed level describing hardware meeting the design goals. Important features of the methodology are: capturing the users concepts, intent, specification, descriptions, constraints and trade-offs; architectural partitioning; what-if analysis at a high level; sizing estimation; timing estimation; architectural trade-off; conceptual design with implementation estimation; and timing closure.

Abstract: A bus bridge circuit having a memory port integrated therewith for upstream memory access independent of the activity on the primary bus connected to the bridge circuit. In a preferred embodiment, the present invention adds a memory port to a PCI bridge circuit usable for upstream data transfers to an attached cache memory subsystem. The memory port of the present invention is preferably 64 bits wide to permit high speed data access to the shared cache memory subsystem. An alternative embodiment of the present invention implements a 128 bit wide data path to an attached high speed cached memory subsystem. The memory port of the present invention utilizes FIFO devices to isolate the memory port transactions from the secondary bus transactions. This FIFO design of the memory port allows bursting of high speed transfers to the shared memory, independent of activity on the primary bus, while minimizing the performance impact on the secondary bus.